diff mbox

[PATCHv2] add nx-842 coproc support

Message ID 1422287432-21358-1-git-send-email-ddstreet@us.ibm.com
State Changes Requested
Headers show

Commit Message

Dan Streetman Jan. 26, 2015, 3:50 p.m. UTC 
Add support for the 842 hw memory compression engine in the NX Coprocessor.
This moves the existing RNG support into its own nx-rng.c file, adds 842
support in a nx-842.c file, and creates a nx-crypto.c file to configure and
disable the crypto engines (which are not supported yet).

New nodes are created for each 842 engine found.  This does not actually
process any of the data or drive the 842 engines, it only configures
registers to set up and enable/disable the engines appropriately, and
creates new nodes so the OS can drive the 842 engines.

Signed-off-by: Dan Streetman <ddstreet@us.ibm.com>
---

v1: https://lists.ozlabs.org/pipermail/skiboot/2015-January/000072.html
Changes since v1 :

Changed CI assignment to overwrite existing value.  Previously an
existing CI was left in place, leading to actual and reported CI
possibly being different, leading to error in kernel driver.

 hw/Makefile.inc |   3 +-
 hw/nx-842.c     | 202 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/nx-crypto.c  | 213 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/nx-rng.c     |  99 ++++++++++++++++++++++++++
 hw/nx.c         | 105 ++--------------------------
 include/nx.h    | 135 +++++++++++++++++++++++++++++++++++
 6 files changed, 657 insertions(+), 100 deletions(-)
 create mode 100644 hw/nx-842.c
 create mode 100644 hw/nx-crypto.c
 create mode 100644 hw/nx-rng.c

Comments

Stewart Smith Feb. 5, 2015, 5:08 a.m. UTC | #1 
A couple of quick thoughts:

Dan Streetman <ddstreet@us.ibm.com> writes:
> Add support for the 842 hw memory compression engine in the NX Coprocessor.
> This moves the existing RNG support into its own nx-rng.c file, adds 842
> support in a nx-842.c file, and creates a nx-crypto.c file to configure and
> disable the crypto engines (which are not supported yet).
>
> New nodes are created for each 842 engine found.  This does not actually
> process any of the data or drive the 842 engines, it only configures
> registers to set up and enable/disable the engines appropriately, and
> creates new nodes so the OS can drive the 842 engines.
>
> diff --git a/hw/nx-842.c b/hw/nx-842.c
> new file mode 100644
> index 0000000..0332e35
> --- /dev/null
> +++ b/hw/nx-842.c
> @@ -0,0 +1,202 @@
<snip>
> +#include <skiboot.h>
> +#include <xscom.h>
> +#include <io.h>
> +#include <cpu.h>
> +#include <nx.h>
> +
> +static u64 nx_842_ci = 1;

This variable name isn't obvious as to what it's used for

> +static int nx_cfg_842(u32 gcid, u64 xcfg, u64 instance)
> +{
> +	u64 cfg, ci, ct;
> +	int rc;
> +
> +	if (instance > NX_P8_842_CFG_CI_MAX) {
> +		prerror("NX%d: ERROR: 842 CI %u exceeds max %u\n",
> +				gcid, (unsigned int)instance,
> +				NX_P8_842_CFG_CI_MAX);
> +		return OPAL_INTERNAL_ERROR;
> +	}
> +
> +	rc = xscom_read(gcid, xcfg, &cfg);
> +	if (rc)
> +		return rc;
> +
> +	ct = GETFIELD(NX_P8_842_CFG_CT, cfg);
> +	if (!ct)
> +		printf("NX%d:   842 CT set to %u\n", gcid, NX_CT_842);
> +	else if (ct == NX_CT_842)
> +		printf("NX%d:   842 CT already set to %u\n", gcid, NX_CT_842);
> +	else
> +		printf("NX%d:   842 CT already set to %u, changing to %u\n",
> +				gcid, (unsigned int)ct, NX_CT_842);

should these be prlog(PR_TRACE or PR_DEBUG instead?



> +	/* Coprocessor Instance must be shifted left.
> +	 * See hw doc Section 5.5.1.
> +	 */
> +	ci = GETFIELD(NX_P8_842_CFG_CI, cfg) >> NX_P8_842_CFG_CI_LSHIFT;
> +	if (!ci)
> +		printf("NX%d:   842 CI set to %u\n", gcid,
> +				(unsigned int)instance);
> +	else if (ci == instance)
> +		printf("NX%d:   842 CI already set to %u\n", gcid,
> +				(unsigned int)instance);
> +	else
> +		printf("NX%d:   842 CI already set to %u, changing to %u\n",
> +				gcid, (unsigned int)ci, (unsigned int)instance);
> +	ci = instance;

same here

> +	cfg = SETFIELD(NX_P8_842_CFG_CI, cfg,
> +			ci << NX_P8_842_CFG_CI_LSHIFT);
> +
> +	/* Enable all functions */
> +	cfg = SETFIELD(NX_P8_842_CFG_FC_ENABLE, cfg, 0x1f);
> +
> +	/* Enable this engine */
> +	cfg |= NX_P8_842_CFG_ENABLE;
> +
> +	rc = xscom_write(gcid, xcfg, cfg);
> +	if (rc)
> +		prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n",
> +				gcid, (unsigned int)ct, (unsigned int)ci, rc);
> +	else
> +		printf("NX%d:   842 Config 0x%016lx\n",
> +				gcid, (unsigned long)cfg);

PR_INFO instead?

> +	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
> +		prerror("NX%d: ERROR: 842 not supported on Power7\n", gcid);
> +		return;

out of interest, is there enough hardware differences that it's a
problem to support on P7? (probably less of an issue as we get more and
more P8s for dev/test)

> diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c
> new file mode 100644
> index 0000000..0683fc0
> --- /dev/null
> +++ b/hw/nx-crypto.c
> @@ -0,0 +1,213 @@
<snip>
> +static int nx_cfg_sym(u32 gcid, u64 xcfg, u64 instance)
> +{
> +	u64 cfg, ci, ct;
> +	int rc;
> +
> +	if (instance > NX_P8_SYM_CFG_CI_MAX) {
> +		prerror("NX%d: ERROR: SYM CI %u exceeds max %u\n",
> +				gcid, (unsigned int)instance,
> +				NX_P8_SYM_CFG_CI_MAX);
> +		return OPAL_INTERNAL_ERROR;
> +	}
<snip>
> +	rc = nx_cfg_sym(gcid, cfg_sym, nx_sym_ci++);
> +	if (rc)
> +		return;
> +
> +	rc = nx_cfg_asym(gcid, cfg_asym, nx_asym_ci++);
> +	if (rc)
> +		return;
> +
> +	rc = nx_cfg_ee(gcid, cfg_ee);
> +	if (rc)
> +		return;
> +
> +	printf("NX%d: Crypto Coprocessors Disabled (not supported)\n", gcid);
> +}

from the look of the flow of things, in any case where cfg fails, we
will *not* print the message saying the coprocessor is disabled.

> +
> +	dt_add_property_strings(rng, "compatible", "ibm,power-rng");
> +	dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr),
> +			hi32(rng_len), lo32(rng_len));
> +	dt_add_property_cells(rng, "ibm,chip-id", gcid);
> +}

It would also be great to document this in doc/device-tree/ too.

> diff --git a/hw/nx.c b/hw/nx.c
> index 8f42717..83528d1 100644
> --- a/hw/nx.c
> +++ b/hw/nx.c
>  void nx_init(void)
>  {
>  	struct dt_node *node;
>
> -	dt_for_each_compatible(dt_root, node, "ibm,power-nx")
> -		nx_create_node(node);
> +	dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
> +		nx_create_rng_node(node);
> +		nx_create_crypto_node(node);
> +		nx_create_842_node(node);
> +	}

Adding to doc/device-tree/ on how 842 is presented to the OS would be
excellent.

We already have (from a dt on a p8):

                nx@2010000 {
                        reg = <0x2010000 0x4000>;
                        phandle = <0x68>;
                        linux,phandle = <0x68>;
                        compatible = "ibm,power-nx", "ibm,power8-nx";
                };

and we're currently exposing this to the OS, so we should document
everything to ensure we a) get it right and b) don't create something
that's confusing.
Dan Streetman Feb. 5, 2015, 7:08 p.m. UTC | #2 
On 2015-02-05 00:08, Stewart Smith wrote:
> A couple of quick thoughts:
> 
> Dan Streetman <ddstreet@us.ibm.com> writes:
>> Add support for the 842 hw memory compression engine in the NX 
>> Coprocessor.
>> This moves the existing RNG support into its own nx-rng.c file, adds 
>> 842
>> support in a nx-842.c file, and creates a nx-crypto.c file to 
>> configure and
>> disable the crypto engines (which are not supported yet).
>> 
>> New nodes are created for each 842 engine found.  This does not 
>> actually
>> process any of the data or drive the 842 engines, it only configures
>> registers to set up and enable/disable the engines appropriately, and
>> creates new nodes so the OS can drive the 842 engines.
>> 
>> diff --git a/hw/nx-842.c b/hw/nx-842.c
>> new file mode 100644
>> index 0000000..0332e35
>> --- /dev/null
>> +++ b/hw/nx-842.c
>> @@ -0,0 +1,202 @@
> <snip>
>> +#include <skiboot.h>
>> +#include <xscom.h>
>> +#include <io.h>
>> +#include <cpu.h>
>> +#include <nx.h>
>> +
>> +static u64 nx_842_ci = 1;
> 
> This variable name isn't obvious as to what it's used for

ok i'll clarify the naming

> 
>> +static int nx_cfg_842(u32 gcid, u64 xcfg, u64 instance)
>> +{
>> +	u64 cfg, ci, ct;
>> +	int rc;
>> +
>> +	if (instance > NX_P8_842_CFG_CI_MAX) {
>> +		prerror("NX%d: ERROR: 842 CI %u exceeds max %u\n",
>> +				gcid, (unsigned int)instance,
>> +				NX_P8_842_CFG_CI_MAX);
>> +		return OPAL_INTERNAL_ERROR;
>> +	}
>> +
>> +	rc = xscom_read(gcid, xcfg, &cfg);
>> +	if (rc)
>> +		return rc;
>> +
>> +	ct = GETFIELD(NX_P8_842_CFG_CT, cfg);
>> +	if (!ct)
>> +		printf("NX%d:   842 CT set to %u\n", gcid, NX_CT_842);
>> +	else if (ct == NX_CT_842)
>> +		printf("NX%d:   842 CT already set to %u\n", gcid, NX_CT_842);
>> +	else
>> +		printf("NX%d:   842 CT already set to %u, changing to %u\n",
>> +				gcid, (unsigned int)ct, NX_CT_842);
> 
> should these be prlog(PR_TRACE or PR_DEBUG instead?

yep, i'll update these and below

> 
> 
> 
>> +	/* Coprocessor Instance must be shifted left.
>> +	 * See hw doc Section 5.5.1.
>> +	 */
>> +	ci = GETFIELD(NX_P8_842_CFG_CI, cfg) >> NX_P8_842_CFG_CI_LSHIFT;
>> +	if (!ci)
>> +		printf("NX%d:   842 CI set to %u\n", gcid,
>> +				(unsigned int)instance);
>> +	else if (ci == instance)
>> +		printf("NX%d:   842 CI already set to %u\n", gcid,
>> +				(unsigned int)instance);
>> +	else
>> +		printf("NX%d:   842 CI already set to %u, changing to %u\n",
>> +				gcid, (unsigned int)ci, (unsigned int)instance);
>> +	ci = instance;
> 
> same here
> 
>> +	cfg = SETFIELD(NX_P8_842_CFG_CI, cfg,
>> +			ci << NX_P8_842_CFG_CI_LSHIFT);
>> +
>> +	/* Enable all functions */
>> +	cfg = SETFIELD(NX_P8_842_CFG_FC_ENABLE, cfg, 0x1f);
>> +
>> +	/* Enable this engine */
>> +	cfg |= NX_P8_842_CFG_ENABLE;
>> +
>> +	rc = xscom_write(gcid, xcfg, cfg);
>> +	if (rc)
>> +		prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n",
>> +				gcid, (unsigned int)ct, (unsigned int)ci, rc);
>> +	else
>> +		printf("NX%d:   842 Config 0x%016lx\n",
>> +				gcid, (unsigned long)cfg);
> 
> PR_INFO instead?
> 
>> +	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
>> +		prerror("NX%d: ERROR: 842 not supported on Power7\n", gcid);
>> +		return;
> 
> out of interest, is there enough hardware differences that it's a
> problem to support on P7? (probably less of an issue as we get more and
> more P8s for dev/test)

no, i just don't have the P7+ doc, and i think it has different register 
addrs there and maybe some other minor differences.  I'll get the P7+ NX 
workbook and I can add support, shouldn't be difficult.

> 
>> diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c
>> new file mode 100644
>> index 0000000..0683fc0
>> --- /dev/null
>> +++ b/hw/nx-crypto.c
>> @@ -0,0 +1,213 @@
> <snip>
>> +static int nx_cfg_sym(u32 gcid, u64 xcfg, u64 instance)
>> +{
>> +	u64 cfg, ci, ct;
>> +	int rc;
>> +
>> +	if (instance > NX_P8_SYM_CFG_CI_MAX) {
>> +		prerror("NX%d: ERROR: SYM CI %u exceeds max %u\n",
>> +				gcid, (unsigned int)instance,
>> +				NX_P8_SYM_CFG_CI_MAX);
>> +		return OPAL_INTERNAL_ERROR;
>> +	}
> <snip>
>> +	rc = nx_cfg_sym(gcid, cfg_sym, nx_sym_ci++);
>> +	if (rc)
>> +		return;
>> +
>> +	rc = nx_cfg_asym(gcid, cfg_asym, nx_asym_ci++);
>> +	if (rc)
>> +		return;
>> +
>> +	rc = nx_cfg_ee(gcid, cfg_ee);
>> +	if (rc)
>> +		return;
>> +
>> +	printf("NX%d: Crypto Coprocessors Disabled (not supported)\n", 
>> gcid);
>> +}
> 
> from the look of the flow of things, in any case where cfg fails, we
> will *not* print the message saying the coprocessor is disabled.

Well, this msg is only printed when the coprocessor is fully configured, 
and we're specifically configuring it to be disabled (we need to at 
least configure its Coprocessor Type value to make it different from the 
842 CT value).  If any of the register config steps fail, it'll print 
out an error message, and then there is no guarantee that the crypto 
coprocessors are actually disabled - they'll be set to whatever they 
happen to default to and/or were set to before.  So printing out a msg 
that they are disabled when a register config failed doesn't seem 
correct - we should only print the error in configuring its register.

> 
>> +
>> +	dt_add_property_strings(rng, "compatible", "ibm,power-rng");
>> +	dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr),
>> +			hi32(rng_len), lo32(rng_len));
>> +	dt_add_property_cells(rng, "ibm,chip-id", gcid);
>> +}
> 
> It would also be great to document this in doc/device-tree/ too.

I didn't do the RNG driver, but sure I can update the doc.

> 
>> diff --git a/hw/nx.c b/hw/nx.c
>> index 8f42717..83528d1 100644
>> --- a/hw/nx.c
>> +++ b/hw/nx.c
>>  void nx_init(void)
>>  {
>>  	struct dt_node *node;
>> 
>> -	dt_for_each_compatible(dt_root, node, "ibm,power-nx")
>> -		nx_create_node(node);
>> +	dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
>> +		nx_create_rng_node(node);
>> +		nx_create_crypto_node(node);
>> +		nx_create_842_node(node);
>> +	}
> 
> Adding to doc/device-tree/ on how 842 is presented to the OS would be
> excellent.

ok.

> 
> We already have (from a dt on a p8):
> 
>                 nx@2010000 {
>                         reg = <0x2010000 0x4000>;
>                         phandle = <0x68>;
>                         linux,phandle = <0x68>;
>                         compatible = "ibm,power-nx", "ibm,power8-nx";
>                 };
> 
> and we're currently exposing this to the OS, so we should document
> everything to ensure we a) get it right and b) don't create something
> that's confusing.

yep that is the node that i use to detect the NX coprocessors.  Should i 
change the 842 node naming to better match that?  e.g. compatible = 
"ibm,power-nx-842" (with the gcid appended for the node name e.g. 
"ibm,power-nx-842#1")
Dan Streetman Feb. 17, 2015, 8:38 p.m. UTC | #3 
This patch set changes the SETFIELD() and GETFIELD() macros to no longer
require the user to specify the _LSH left shift value, since that can be
determined from the _MASK.  It also adds support for the nx-842
coprocessor.

--

Techinically, the field macro change isn't related to the nx-842 support.
But I'd like to get the nx-842 support in soon :-)  I can break this apart
if you'd prefer.

Sorry if you have got more than 1 copy of this, I don't think my mailer sent
it out to anyone the first time.


Dan Streetman (5):
  simplify GET/SETFIELD() use, add MASK_TO_LSH()
  Change user-defined _MASK/_LSH to just mask
  update users of GET/SETFIELD()
  change direct use of LSH to SETFIELD
  add nx-842 coproc support

 doc/device-tree/nx.txt |  47 +++++++++
 hw/Makefile.inc        |   3 +-
 hw/chiptod.c           |   3 +-
 hw/lpc.c               |  27 ++---
 hw/nx-842.c            | 212 +++++++++++++++++++++++++++++++++++++
 hw/nx-crypto.c         | 277 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/nx-rng.c            |  99 ++++++++++++++++++
 hw/nx.c                | 105 ++-----------------
 hw/p5ioc2-phb.c        |   7 +-
 hw/p5ioc2.c            |   2 +-
 hw/p7ioc-phb.c         |  14 +--
 hw/p8-i2c.c            |  47 +++------
 hw/phb3.c              |   8 +-
 hw/xscom.c             |  24 ++---
 include/bitutils.h     |  11 +-
 include/gx.h           |  18 ++--
 include/nx.h           | 151 +++++++++++++++++++++++++++
 include/p5ioc2-regs.h  |  51 +++------
 include/p7ioc-regs.h   | 135 ++++++++----------------
 include/pci-cfg.h      | 116 +++++++--------------
 include/phb3-regs.h    | 157 ++++++++++------------------
 include/processor.h    |  30 ++----
 include/psi.h          |   6 +-
 23 files changed, 1029 insertions(+), 521 deletions(-)
 create mode 100644 doc/device-tree/nx.txt
 create mode 100644 hw/nx-842.c
 create mode 100644 hw/nx-crypto.c
 create mode 100644 hw/nx-rng.c
diff mbox

Patch

diff --git a/hw/Makefile.inc b/hw/Makefile.inc
index 83125be..416d23c 100644
--- a/hw/Makefile.inc
+++ b/hw/Makefile.inc
@@ -2,7 +2,8 @@ 
 
 SUBDIRS += hw
 HW_OBJS  = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o
-HW_OBJS += homer.o slw.o occ.o nx.o fsi-master.o centaur.o
+HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o
+HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-842.o
 HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o p5ioc2.o p5ioc2-phb.o
 HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o
 HW=hw/built-in.o
diff --git a/hw/nx-842.c b/hw/nx-842.c
new file mode 100644
index 0000000..0332e35
--- /dev/null
+++ b/hw/nx-842.c
@@ -0,0 +1,202 @@ 
+/* Copyright 2015 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+
+#include <skiboot.h>
+#include <xscom.h>
+#include <io.h>
+#include <cpu.h>
+#include <nx.h>
+
+static u64 nx_842_ci = 1;
+
+static int nx_cfg_842(u32 gcid, u64 xcfg, u64 instance)
+{
+	u64 cfg, ci, ct;
+	int rc;
+
+	if (instance > NX_P8_842_CFG_CI_MAX) {
+		prerror("NX%d: ERROR: 842 CI %u exceeds max %u\n",
+				gcid, (unsigned int)instance,
+				NX_P8_842_CFG_CI_MAX);
+		return OPAL_INTERNAL_ERROR;
+	}
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	ct = GETFIELD(NX_P8_842_CFG_CT, cfg);
+	if (!ct)
+		printf("NX%d:   842 CT set to %u\n", gcid, NX_CT_842);
+	else if (ct == NX_CT_842)
+		printf("NX%d:   842 CT already set to %u\n", gcid, NX_CT_842);
+	else
+		printf("NX%d:   842 CT already set to %u, changing to %u\n",
+				gcid, (unsigned int)ct, NX_CT_842);
+	ct = NX_CT_842;
+	cfg = SETFIELD(NX_P8_842_CFG_CT, cfg, ct);
+
+	/* Coprocessor Instance must be shifted left.
+	 * See hw doc Section 5.5.1.
+	 */
+	ci = GETFIELD(NX_P8_842_CFG_CI, cfg) >> NX_P8_842_CFG_CI_LSHIFT;
+	if (!ci)
+		printf("NX%d:   842 CI set to %u\n", gcid,
+				(unsigned int)instance);
+	else if (ci == instance)
+		printf("NX%d:   842 CI already set to %u\n", gcid,
+				(unsigned int)instance);
+	else
+		printf("NX%d:   842 CI already set to %u, changing to %u\n",
+				gcid, (unsigned int)ci, (unsigned int)instance);
+	ci = instance;
+	cfg = SETFIELD(NX_P8_842_CFG_CI, cfg,
+			ci << NX_P8_842_CFG_CI_LSHIFT);
+
+	/* Enable all functions */
+	cfg = SETFIELD(NX_P8_842_CFG_FC_ENABLE, cfg, 0x1f);
+
+	/* Enable this engine */
+	cfg |= NX_P8_842_CFG_ENABLE;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: 842 CT %u CI %u config failure %d\n",
+				gcid, (unsigned int)ct, (unsigned int)ci, rc);
+	else
+		printf("NX%d:   842 Config 0x%016lx\n",
+				gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+static int nx_cfg_dma(u32 gcid, u64 xcfg)
+{
+	u64 cfg;
+	int rc;
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	if (NX_DMA_842_COMPRESS_PREFETCH)
+		cfg = cfg | NX_P8_DMA_CFG_842_COMPRESS_PREFETCH;
+	if (NX_DMA_842_DECOMPRESS_PREFETCH)
+		cfg = cfg | NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH;
+
+	cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPRESS_MAX_RR, cfg,
+			NX_DMA_842_COMPRESS_MAX_RR);
+	cfg = SETFIELD(NX_P8_DMA_CFG_842_DECOMPRESS_MAX_RR, cfg,
+			NX_DMA_842_DECOMPRESS_MAX_RR);
+
+	if (NX_DMA_842_SPBC)
+		cfg = cfg | NX_P8_DMA_CFG_842_SPBC;
+
+	cfg = SETFIELD(NX_P8_DMA_CFG_842_CSB_WR, cfg,
+			NX_DMA_842_CSB_WR);
+	cfg = SETFIELD(NX_P8_DMA_CFG_842_COMPLETION_MODE, cfg,
+			NX_DMA_842_COMPLETION_MODE);
+	cfg = SETFIELD(NX_P8_DMA_CFG_842_CPB_WR, cfg,
+			NX_DMA_842_CPB_WR);
+	if (NX_DMA_842_OUTPUT_WR)
+		cfg = cfg | NX_P8_DMA_CFG_842_OUTPUT_DATA_WR;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
+	else
+		printf("NX%d:   DMA 0x%016lx\n", gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+static int nx_cfg_ee(u32 gcid, u64 xcfg)
+{
+	u64 cfg;
+	int rc;
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	cfg |= NX_P8_EE_CFG_842_1;
+	cfg |= NX_P8_EE_CFG_842_0;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
+	else
+		printf("NX%d:   Engine Enable 0x%016lx\n",
+				gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+void nx_create_842_node(struct dt_node *node)
+{
+	u32 gcid;
+	u32 pb_base;
+	u64 cfg_842, cfg_ee, cfg_dma;
+	u64 instance;
+	struct dt_node *dt_842;
+	int rc;
+	char node_name[32];
+
+	gcid = dt_get_chip_id(node);
+	pb_base = dt_get_address(node, 0, NULL);
+
+	printf("NX%d: 842 at 0x%x\n", gcid, pb_base);
+
+	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
+		prerror("NX%d: ERROR: 842 not supported on Power7\n", gcid);
+		return;
+	} else if (dt_node_is_compatible(node, "ibm,power8-nx")) {
+		cfg_842 = pb_base + NX_P8_842_CFG;
+		cfg_ee = pb_base + NX_P8_EE_CFG;
+		cfg_dma = pb_base + NX_P8_DMA_CFG;
+	} else {
+		prerror("NX%d: ERROR: Unknown NX type!\n", gcid);
+		return;
+	}
+
+	rc = nx_cfg_dma(gcid, cfg_dma);
+	if (rc)
+		return;
+
+	instance = nx_842_ci++;
+	rc = nx_cfg_842(gcid, cfg_842, instance);
+	if (rc)
+		return;
+
+	rc = nx_cfg_ee(gcid, cfg_ee);
+	if (rc)
+		return;
+
+	printf("NX%d: 842 Coprocessor Enabled\n", gcid);
+
+	snprintf(node_name, sizeof(node_name),
+			"ibm,nx842-powernv-v1#%d", gcid);
+	dt_842 = dt_new(dt_root, node_name);
+	if (!dt_842)
+		return;
+
+	dt_add_property_strings(dt_842, "compatible", "ibm,nx842-powernv");
+	dt_add_property_cells(dt_842, "ibm,chip-id", gcid);
+	dt_add_property_cells(dt_842, "ibm,coprocessor-type", NX_CT_842);
+	dt_add_property_cells(dt_842, "ibm,coprocessor-instance", instance);
+}
diff --git a/hw/nx-crypto.c b/hw/nx-crypto.c
new file mode 100644
index 0000000..0683fc0
--- /dev/null
+++ b/hw/nx-crypto.c
@@ -0,0 +1,213 @@ 
+/* Copyright 2015 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+
+#include <skiboot.h>
+#include <xscom.h>
+#include <io.h>
+#include <cpu.h>
+#include <nx.h>
+
+static u64 nx_sym_ci = 1;
+static u64 nx_asym_ci = 1;
+
+static int nx_cfg_sym(u32 gcid, u64 xcfg, u64 instance)
+{
+	u64 cfg, ci, ct;
+	int rc;
+
+	if (instance > NX_P8_SYM_CFG_CI_MAX) {
+		prerror("NX%d: ERROR: SYM CI %u exceeds max %u\n",
+				gcid, (unsigned int)instance,
+				NX_P8_SYM_CFG_CI_MAX);
+		return OPAL_INTERNAL_ERROR;
+	}
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	ct = GETFIELD(NX_P8_SYM_CFG_CT, cfg);
+	if (!ct)
+		printf("NX%d:   SYM CT set to %u\n", gcid, NX_CT_SYM);
+	else if (ct == NX_CT_SYM)
+		printf("NX%d:   SYM CT already set to %u\n", gcid, NX_CT_SYM);
+	else
+		printf("NX%d:   SYM CT already set to %u, changing to %u\n",
+				gcid, (unsigned int)ct, NX_CT_SYM);
+	ct = NX_CT_SYM;
+	cfg = SETFIELD(NX_P8_SYM_CFG_CT, cfg, ct);
+
+	/* Coprocessor Instance must be shifted left.
+	 * See hw doc Section 5.5.1.
+	 */
+	ci = GETFIELD(NX_P8_SYM_CFG_CI, cfg) >> NX_P8_SYM_CFG_CI_LSHIFT;
+	if (!ci)
+		printf("NX%d:   SYM CI set to %u\n", gcid,
+				(unsigned int)instance);
+	else if (ci == instance)
+		printf("NX%d:   SYM CI already set to %u\n", gcid,
+				(unsigned int)instance);
+	else
+		printf("NX%d:   SYM CI already set to %u, changing to %u\n",
+				gcid, (unsigned int)ci, (unsigned int)instance);
+	ci = instance;
+	cfg = SETFIELD(NX_P8_SYM_CFG_CI, cfg,
+			ci << NX_P8_SYM_CFG_CI_LSHIFT);
+
+	/* Disable all functions until supported */
+	cfg = SETFIELD(NX_P8_SYM_CFG_FC_ENABLE, cfg, 0);
+
+	/* Disable this engine, not supported yet */
+	cfg &= ~NX_P8_SYM_CFG_ENABLE;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: SYM CT %u CI %u config failure %d\n",
+				gcid, (unsigned int)ct, (unsigned int)ci, rc);
+	else
+		printf("NX%d:   SYM Config 0x%016lx\n",
+				gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+static int nx_cfg_asym(u32 gcid, u64 xcfg, u64 instance)
+{
+	u64 cfg, ci, ct;
+	int rc;
+
+	if (instance > NX_P8_ASYM_CFG_CI_MAX) {
+		prerror("NX%d: ERROR: ASYM CI %u exceeds max %u\n",
+				gcid, (unsigned int)instance,
+				NX_P8_ASYM_CFG_CI_MAX);
+		return OPAL_INTERNAL_ERROR;
+	}
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	ct = GETFIELD(NX_P8_ASYM_CFG_CT, cfg);
+	if (!ct)
+		printf("NX%d:   ASYM CT set to %u\n", gcid, NX_CT_ASYM);
+	else if (ct == NX_CT_ASYM)
+		printf("NX%d:   ASYM CT already set to %u\n", gcid, NX_CT_ASYM);
+	else
+		printf("NX%d:   ASYM CT already set to %u, changing to %u\n",
+				gcid, (unsigned int)ct, NX_CT_ASYM);
+	ct = NX_CT_ASYM;
+	cfg = SETFIELD(NX_P8_ASYM_CFG_CT, cfg, ct);
+
+	/* Coprocessor Instance must be shifted left.
+	 * See hw doc Section 5.5.1.
+	 */
+	ci = GETFIELD(NX_P8_ASYM_CFG_CI, cfg) >> NX_P8_ASYM_CFG_CI_LSHIFT;
+	if (!ci)
+		printf("NX%d:   ASYM CI set to %u\n", gcid,
+				(unsigned int)instance);
+	else if (ci == instance)
+		printf("NX%d:   ASYM CI already set to %u\n", gcid,
+				(unsigned int)instance);
+	else
+		printf("NX%d:   ASYM CI already set to %u, changing to %u\n",
+				gcid, (unsigned int)ci, (unsigned int)instance);
+	ci = instance;
+	cfg = SETFIELD(NX_P8_ASYM_CFG_CI, cfg,
+			ci << NX_P8_ASYM_CFG_CI_LSHIFT);
+
+	/* Disable all functions until supported */
+	cfg = SETFIELD(NX_P8_ASYM_CFG_FC_ENABLE, cfg, 0);
+
+	/* Disable this engine, not supported yet */
+	cfg &= ~NX_P8_ASYM_CFG_ENABLE;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: ASYM CT %u CI %u config failure %d\n",
+				gcid, (unsigned int)ct, (unsigned int)ci, rc);
+	else
+		printf("NX%d:   ASYM Config 0x%016lx\n",
+				gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+static int nx_cfg_ee(u32 gcid, u64 xcfg)
+{
+	u64 cfg;
+	int rc;
+
+	rc = xscom_read(gcid, xcfg, &cfg);
+	if (rc)
+		return rc;
+
+	cfg &= ~NX_P8_EE_CFG_AMF_3;
+	cfg &= ~NX_P8_EE_CFG_AMF_2;
+	cfg &= ~NX_P8_EE_CFG_AMF_1;
+	cfg &= ~NX_P8_EE_CFG_AMF_0;
+	cfg &= ~NX_P8_EE_CFG_SYM_1;
+	cfg &= ~NX_P8_EE_CFG_SYM_0;
+
+	rc = xscom_write(gcid, xcfg, cfg);
+	if (rc)
+		prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
+	else
+		printf("NX%d:   Engine Enable 0x%016lx\n",
+				gcid, (unsigned long)cfg);
+
+	return rc;
+}
+
+void nx_create_crypto_node(struct dt_node *node)
+{
+	u32 gcid;
+	u32 pb_base;
+	u64 cfg_sym, cfg_asym, cfg_ee;
+	int rc;
+
+	gcid = dt_get_chip_id(node);
+	pb_base = dt_get_address(node, 0, NULL);
+
+	printf("NX%d: Crypto at 0x%x\n", gcid, pb_base);
+
+	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
+		prerror("NX%d: ERROR: Crypto not supported on Power7\n", gcid);
+		return;
+	} else if (dt_node_is_compatible(node, "ibm,power8-nx")) {
+		cfg_sym = pb_base + NX_P8_SYM_CFG;
+		cfg_asym = pb_base + NX_P8_ASYM_CFG;
+		cfg_ee = pb_base + NX_P8_EE_CFG;
+	} else {
+		prerror("NX%d: ERROR: Unknown NX type!\n", gcid);
+		return;
+	}
+
+	rc = nx_cfg_sym(gcid, cfg_sym, nx_sym_ci++);
+	if (rc)
+		return;
+
+	rc = nx_cfg_asym(gcid, cfg_asym, nx_asym_ci++);
+	if (rc)
+		return;
+
+	rc = nx_cfg_ee(gcid, cfg_ee);
+	if (rc)
+		return;
+
+	printf("NX%d: Crypto Coprocessors Disabled (not supported)\n", gcid);
+}
diff --git a/hw/nx-rng.c b/hw/nx-rng.c
new file mode 100644
index 0000000..c4980b9
--- /dev/null
+++ b/hw/nx-rng.c
@@ -0,0 +1,99 @@ 
+/* Copyright 2013-2015 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * 	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+
+#include <skiboot.h>
+#include <xscom.h>
+#include <io.h>
+#include <cpu.h>
+#include <nx.h>
+
+void nx_create_rng_node(struct dt_node *node)
+{
+	u64 bar, cfg;
+	u64 xbar, xcfg;
+	u32 pb_base;
+	u32 gcid;
+	u64 rng_addr, rng_len, len;
+	struct dt_node *rng;
+	int rc;
+
+	gcid = dt_get_chip_id(node);
+	pb_base = dt_get_address(node, 0, NULL);
+
+	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
+		xbar = pb_base + NX_P7_RNG_BAR;
+		xcfg = pb_base + NX_P7_RNG_CFG;
+	} else if (dt_node_is_compatible(node, "ibm,power8-nx")) {
+		xbar = pb_base + NX_P8_RNG_BAR;
+		xcfg = pb_base + NX_P8_RNG_CFG;
+	} else {
+		prerror("NX%d: Unknown NX type!\n", gcid);
+		return;
+	}
+
+	rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */
+	if (rc)
+		return;	/* Hope xscom always prints error message */
+
+	rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */
+	if (rc)
+		return;
+
+	/*
+	 * We use the P8 BAR constants. The layout of the BAR is the
+	 * same, with more bits at the top of P8 which are hard wired to
+	 * 0 on P7. We also mask in-place rather than using GETFIELD
+	 * for the base address as we happen to *know* that it's properly
+	 * aligned in the register.
+	 *
+	 * FIXME? Always assusme BAR gets a valid address from FSP
+	 */
+	rng_addr = bar & NX_P8_RNG_BAR_ADDR_MASK;
+	len  = GETFIELD(NX_P8_RNG_BAR_SIZE, bar);
+	if (len > 4) {
+		prerror("NX%d: Corrupted bar size %lld\n", gcid, len);
+		return;
+	}
+	rng_len = (u64[]){  0x1000,         /* 4K */
+			    0x10000,        /* 64K */
+			    0x400000000,    /* 16G*/
+			    0x100000,       /* 1M */
+			    0x1000000       /* 16M */} [len];
+
+
+	printf("NX%d: RNG BAR set to 0x%016llx..0x%016llx\n",
+	       gcid, rng_addr, rng_addr + rng_len - 1);
+
+	/* RNG must be enabled before MMIO is enabled */
+	rc = xscom_write(gcid, xcfg, cfg | NX_P8_RNG_CFG_ENABLE);
+	if (rc)
+		return;
+
+	/* The BAR needs to be enabled too */
+	rc = xscom_write(gcid, xbar, bar | NX_P8_RNG_BAR_ENABLE);
+	if (rc)
+		return;
+	rng = dt_new_addr(dt_root, "hwrng", rng_addr);
+	if (!rng)
+		return;
+
+	dt_add_property_strings(rng, "compatible", "ibm,power-rng");
+	dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr),
+			hi32(rng_len), lo32(rng_len));
+	dt_add_property_cells(rng, "ibm,chip-id", gcid);
+}
diff --git a/hw/nx.c b/hw/nx.c
index 8f42717..83528d1 100644
--- a/hw/nx.c
+++ b/hw/nx.c
@@ -1,4 +1,4 @@ 
-/* Copyright 2013-2014 IBM Corp.
+/* Copyright 2013-2015 IBM Corp.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -22,106 +22,13 @@ 
 #include <cpu.h>
 #include <nx.h>
 
-#define NX_P7_RNG_BAR		XSCOM_SAT(0x1, 0x2, 0x0c)
-#define   NX_P7_RNG_BAR_ADDR_MASK	PPC_BITMASK(18, 51)
-#define   NX_P7_RNG_BAR_ADDR_LSH	PPC_BITLSHIFT(51)
-#define   NX_P7_RNG_BAR_SIZE_MASK	PPC_BITMASK(53, 55)
-#define   NX_P7_RNG_BAR_SIZE_LSH	PPC_BITLSHIFT(55)
-#define   NX_P7_RNG_BAR_ENABLE		PPC_BIT(52)
-
-#define NX_P8_RNG_BAR		XSCOM_SAT(0xc, 0x2, 0x0d)
-#define   NX_P8_RNG_BAR_ADDR_MASK	PPC_BITMASK(14, 51)
-#define   NX_P8_RNG_BAR_ADDR_LSH	PPC_BITLSHIFT(51)
-#define   NX_P8_RNG_BAR_SIZE_MASK	PPC_BITMASK(53, 55)
-#define   NX_P8_RNG_BAR_SIZE_LSH	PPC_BITLSHIFT(55)
-#define   NX_P8_RNG_BAR_ENABLE		PPC_BIT(52)
-
-#define NX_P7_RNG_CFG		XSCOM_SAT(0x1, 0x2, 0x12)
-#define   NX_P7_RNG_CFG_ENABLE		PPC_BIT(63)
-#define NX_P8_RNG_CFG		XSCOM_SAT(0xc, 0x2, 0x12)
-#define   NX_P8_RNG_CFG_ENABLE		PPC_BIT(63)
-
-static void nx_create_node(struct dt_node *node)
-{
-	u64 bar, cfg;
-	u64 xbar, xcfg;
-	u32 pb_base;
-	u32 gcid;
-	u64 rng_addr, rng_len, len;
-	struct dt_node *rng;
-	int rc;
-
-	gcid = dt_get_chip_id(node);
-	pb_base = dt_get_address(node, 0, NULL);
-
-	if (dt_node_is_compatible(node, "ibm,power7-nx")) {
-		xbar = pb_base + NX_P7_RNG_BAR;
-		xcfg = pb_base + NX_P7_RNG_CFG;
-	} else if (dt_node_is_compatible(node, "ibm,power8-nx")) {
-		xbar = pb_base + NX_P8_RNG_BAR;
-		xcfg = pb_base + NX_P8_RNG_CFG;
-	} else {
-		prerror("NX%d: Unknown NX type!\n", gcid);
-		return;
-	}
-
-	rc = xscom_read(gcid, xbar, &bar); /* Get RNG BAR */
-	if (rc)
-		return;	/* Hope xscom always prints error message */
-
-	rc = xscom_read(gcid, xcfg, &cfg); /* Get RNG CFG */
-	if (rc)
-		return;
-
-	/*
-	 * We use the P8 BAR constants. The layout of the BAR is the
-	 * same, with more bits at the top of P8 which are hard wired to
-	 * 0 on P7. We also mask in-place rather than using GETFIELD
-	 * for the base address as we happen to *know* that it's properly
-	 * aligned in the register.
-	 *
-	 * FIXME? Always assusme BAR gets a valid address from FSP
-	 */
-	rng_addr = bar & NX_P8_RNG_BAR_ADDR_MASK;
-	len  = GETFIELD(NX_P8_RNG_BAR_SIZE, bar);
-	if (len > 4) {
-		prerror("NX%d: Corrupted bar size %lld\n", gcid, len);
-		return;
-	}
-	rng_len = (u64[]){  0x1000,         /* 4K */
-			    0x10000,        /* 64K */
-			    0x400000000,    /* 16G*/
-			    0x100000,       /* 1M */
-			    0x1000000       /* 16M */} [len];
-
-
-	printf("NX%d: RNG BAR set to 0x%016llx..0x%016llx\n",
-	       gcid, rng_addr, rng_addr + rng_len - 1);
-
-	/* RNG must be enabled before MMIO is enabled */
-	rc = xscom_write(gcid, xcfg, cfg | NX_P8_RNG_CFG_ENABLE);
-	if (rc)
-		return;
-
-	/* The BAR needs to be enabled too */
-	rc = xscom_write(gcid, xbar, bar | NX_P8_RNG_BAR_ENABLE);
-	if (rc)
-		return;
-	rng = dt_new_addr(dt_root, "hwrng", rng_addr);
-	if (!rng)
-		return;
-
-	dt_add_property_strings(rng, "compatible", "ibm,power-rng");
-	dt_add_property_cells(rng, "reg", hi32(rng_addr), lo32(rng_addr),
-			hi32(rng_len), lo32(rng_len));
-	dt_add_property_cells(rng, "ibm,chip-id", gcid);
-}
-
-/* Create nodes for MMIO accesible components in NX (only RNG) */
 void nx_init(void)
 {
 	struct dt_node *node;
 
-	dt_for_each_compatible(dt_root, node, "ibm,power-nx")
-		nx_create_node(node);
+	dt_for_each_compatible(dt_root, node, "ibm,power-nx") {
+		nx_create_rng_node(node);
+		nx_create_crypto_node(node);
+		nx_create_842_node(node);
+	}
 }
diff --git a/include/nx.h b/include/nx.h
index ef02ed5..d742995 100644
--- a/include/nx.h
+++ b/include/nx.h
@@ -17,6 +17,141 @@ 
 #ifndef __NX_H
 #define __NX_H
 
+/* Random Number Generator */
+#define NX_P7_RNG_BAR		XSCOM_SAT(0x1, 0x2, 0x0c)
+#define   NX_P7_RNG_BAR_ADDR_MASK	PPC_BITMASK(18, 51)
+#define   NX_P7_RNG_BAR_ADDR_LSH	PPC_BITLSHIFT(51)
+#define   NX_P7_RNG_BAR_SIZE_MASK	PPC_BITMASK(53, 55)
+#define   NX_P7_RNG_BAR_SIZE_LSH	PPC_BITLSHIFT(55)
+#define   NX_P7_RNG_BAR_ENABLE		PPC_BIT(52)
+#define NX_P8_RNG_BAR		XSCOM_SAT(0xc, 0x2, 0x0d)
+#define   NX_P8_RNG_BAR_ADDR_MASK	PPC_BITMASK(14, 51)
+#define   NX_P8_RNG_BAR_ADDR_LSH	PPC_BITLSHIFT(51)
+#define   NX_P8_RNG_BAR_SIZE_MASK	PPC_BITMASK(53, 55)
+#define   NX_P8_RNG_BAR_SIZE_LSH	PPC_BITLSHIFT(55)
+#define   NX_P8_RNG_BAR_ENABLE		PPC_BIT(52)
+
+#define NX_P7_RNG_CFG		XSCOM_SAT(0x1, 0x2, 0x12)
+#define   NX_P7_RNG_CFG_ENABLE		PPC_BIT(63)
+#define NX_P8_RNG_CFG		XSCOM_SAT(0xc, 0x2, 0x12)
+#define   NX_P8_RNG_CFG_ENABLE		PPC_BIT(63)
+
+
+/* Symmetric Crypto */
+#define NX_P8_SYM_CFG		XSCOM_SAT(0xc, 0x2, 0x0a)
+#define   NX_P8_SYM_CFG_CI_MASK		PPC_BITMASK(2, 14)
+#define   NX_P8_SYM_CFG_CI_LSH		PPC_BITLSHIFT(14)
+#define   NX_P8_SYM_CFG_CT_MASK		PPC_BITMASK(18, 23)
+#define   NX_P8_SYM_CFG_CT_LSH		PPC_BITLSHIFT(23)
+#define   NX_P8_SYM_CFG_FC_ENABLE_MASK	PPC_BITMASK(32, 39)
+#define   NX_P8_SYM_CFG_FC_ENABLE_LSH	PPC_BITLSHIFT(39)
+#define   NX_P8_SYM_CFG_ENABLE		PPC_BIT(63)
+
+
+/* Asymmetric Crypto */
+#define NX_P8_ASYM_CFG		XSCOM_SAT(0xc, 0x2, 0x0b)
+#define   NX_P8_ASYM_CFG_CI_MASK	PPC_BITMASK(2, 14)
+#define   NX_P8_ASYM_CFG_CI_LSH		PPC_BITLSHIFT(14)
+#define   NX_P8_ASYM_CFG_CT_MASK	PPC_BITMASK(18, 23)
+#define   NX_P8_ASYM_CFG_CT_LSH		PPC_BITLSHIFT(23)
+#define   NX_P8_ASYM_CFG_FC_ENABLE_MASK	PPC_BITMASK(32, 52)
+#define   NX_P8_ASYM_CFG_FC_ENABLE_LSH	PPC_BITLSHIFT(52)
+#define   NX_P8_ASYM_CFG_ENABLE		PPC_BIT(63)
+
+
+/* 842 Compression */
+#define NX_P8_842_CFG		XSCOM_SAT(0xc, 0x2, 0x0c)
+#define   NX_P8_842_CFG_CI_MASK		PPC_BITMASK(2, 14)
+#define   NX_P8_842_CFG_CI_LSH		PPC_BITLSHIFT(14)
+#define   NX_P8_842_CFG_CT_MASK		PPC_BITMASK(18, 23)
+#define   NX_P8_842_CFG_CT_LSH		PPC_BITLSHIFT(23)
+#define   NX_P8_842_CFG_FC_ENABLE_MASK	PPC_BITMASK(32, 36)
+#define   NX_P8_842_CFG_FC_ENABLE_LSH	PPC_BITLSHIFT(36)
+#define   NX_P8_842_CFG_ENABLE		PPC_BIT(63)
+
+
+/* DMA */
+#define NX_P8_DMA_CFG		XSCOM_SAT(0xc, 0x1, 0x02)
+#define   NX_P8_DMA_CFG_842_COMPRESS_PREFETCH		PPC_BIT(23)
+#define   NX_P8_DMA_CFG_842_DECOMPRESS_PREFETCH		PPC_BIT(24)
+#define   NX_P8_DMA_CFG_AES_SHA_MAX_RR_MASK		PPC_BITMASK(25, 28)
+#define   NX_P8_DMA_CFG_AES_SHA_MAX_RR_LSH		PPC_BITLSHIFT(28)
+#define   NX_P8_DMA_CFG_AMF_MAX_RR_MASK			PPC_BITMASK(29, 32)
+#define   NX_P8_DMA_CFG_AMF_MAX_RR_LSH			PPC_BITLSHIFT(32)
+#define   NX_P8_DMA_CFG_842_COMPRESS_MAX_RR_MASK	PPC_BITMASK(33, 36)
+#define   NX_P8_DMA_CFG_842_COMPRESS_MAX_RR_LSH		PPC_BITLSHIFT(36)
+#define   NX_P8_DMA_CFG_842_DECOMPRESS_MAX_RR_MASK	PPC_BITMASK(37, 40)
+#define   NX_P8_DMA_CFG_842_DECOMPRESS_MAX_RR_LSH	PPC_BITLSHIFT(40)
+#define   NX_P8_DMA_CFG_AES_SHA_CSB_WR_MASK		PPC_BITMASK(41, 42)
+#define   NX_P8_DMA_CFG_AES_SHA_CSB_WR_LSH		PPC_BITLSHIFT(42)
+#define   NX_P8_DMA_CFG_AES_SHA_COMPLETION_MODE_MASK	PPC_BITMASK(43, 44)
+#define   NX_P8_DMA_CFG_AES_SHA_COMPLETION_MODE_LSH	PPC_BITLSHIFT(44)
+#define   NX_P8_DMA_CFG_AES_SHA_CPB_WR_MASK		PPC_BITMASK(45, 46)
+#define   NX_P8_DMA_CFG_AES_SHA_CPB_WR_LSH		PPC_BITLSHIFT(46)
+#define   NX_P8_DMA_CFG_AES_SHA_OUTPUT_DATA_WR		PPC_BIT(47)
+#define   NX_P8_DMA_CFG_AMF_CSB_WR_MASK			PPC_BITMASK(49, 50)
+#define   NX_P8_DMA_CFG_AMF_CSB_WR_LSH			PPC_BITLSHIFT(50)
+#define   NX_P8_DMA_CFG_AMF_COMPLETION_MODE_MASK	PPC_BITMASK(51, 52)
+#define   NX_P8_DMA_CFG_AMF_COMPLETION_MODE_LSH		PPC_BITLSHIFT(52)
+#define   NX_P8_DMA_CFG_AMF_CPB_WR_MASK			PPC_BITMASK(53, 54)
+#define   NX_P8_DMA_CFG_AMF_CPB_WR_LSH			PPC_BITLSHIFT(54)
+#define   NX_P8_DMA_CFG_AMF_OUTPUT_DATA_WR		PPC_BIT(55)
+#define   NX_P8_DMA_CFG_842_SPBC			PPC_BIT(56)
+#define   NX_P8_DMA_CFG_842_CSB_WR_MASK			PPC_BITMASK(57, 58)
+#define   NX_P8_DMA_CFG_842_CSB_WR_LSH			PPC_BITLSHIFT(58)
+#define   NX_P8_DMA_CFG_842_COMPLETION_MODE_MASK	PPC_BITMASK(59, 60)
+#define   NX_P8_DMA_CFG_842_COMPLETION_MODE_LSH		PPC_BITLSHIFT(60)
+#define   NX_P8_DMA_CFG_842_CPB_WR_MASK			PPC_BITMASK(61, 62)
+#define   NX_P8_DMA_CFG_842_CPB_WR_LSH			PPC_BITLSHIFT(62)
+#define   NX_P8_DMA_CFG_842_OUTPUT_DATA_WR		PPC_BIT(63)
+
+
+/* Engine Enable Register */
+#define NX_P8_EE_CFG	XSCOM_SAT(0xc, 0x1, 0x01)
+#define   NX_P8_EE_CFG_EFUSE	PPC_BIT(0)
+#define   NX_P8_EE_CFG_AMF_3	PPC_BIT(53)
+#define   NX_P8_EE_CFG_AMF_2	PPC_BIT(54)
+#define   NX_P8_EE_CFG_AMF_1	PPC_BIT(55)
+#define   NX_P8_EE_CFG_AMF_0	PPC_BIT(56)
+#define   NX_P8_EE_CFG_SYM_1	PPC_BIT(57)
+#define   NX_P8_EE_CFG_SYM_0	PPC_BIT(58)
+#define   NX_P8_EE_CFG_842_1	PPC_BIT(62)
+#define   NX_P8_EE_CFG_842_0	PPC_BIT(63)
+
+
+/* Configuration parameters */
+#define NX_DMA_842_COMPRESS_PREFETCH	1
+#define NX_DMA_842_DECOMPRESS_PREFETCH	1
+#define NX_DMA_842_COMPRESS_MAX_RR	1
+#define NX_DMA_842_DECOMPRESS_MAX_RR	1
+#define NX_DMA_842_SPBC			1
+#define NX_DMA_842_CSB_WR		0
+#define NX_DMA_842_COMPLETION_MODE	0
+#define NX_DMA_842_CPB_WR		0
+#define NX_DMA_842_OUTPUT_WR		0
+
+
+/* Arbitrary Coprocessor Type values */
+#define NX_CT_SYM	1
+#define NX_CT_ASYM	2
+#define NX_CT_842	3
+
+
+/* Coprocessor Instance counter
+ * P8 NX workbook, section 5.5.1
+ * "Assigning <CT,CI> Values"
+ */
+#define NX_P8_SYM_CFG_CI_MAX		511
+#define NX_P8_SYM_CFG_CI_LSHIFT		2
+#define NX_P8_ASYM_CFG_CI_MAX		127
+#define NX_P8_ASYM_CFG_CI_LSHIFT	4
+#define NX_P8_842_CFG_CI_MAX		511
+#define NX_P8_842_CFG_CI_LSHIFT		2
+
+extern void nx_create_rng_node(struct dt_node *);
+extern void nx_create_crypto_node(struct dt_node *);
+extern void nx_create_842_node(struct dt_node *);
+
 extern void nx_init(void);
 
 #endif /* __NX_H */