[01/11] target-mips: add ISAMode bits for mips16 execution

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
---
 target-mips/cpu.h       |    1 +
 target-mips/translate.c |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)

On Mon, Nov 23, 2009 at 12:49:59PM -0800, Nathan Froyd wrote:
> 
> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
>  target-mips/cpu.h       |    1 +
>  target-mips/translate.c |    2 ++
>  2 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 82f9a38..e8febe6 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -167,6 +167,7 @@ struct TCState {
>      target_ulong CP0_TCContext;
>      target_ulong CP0_TCSchedule;
>      target_ulong CP0_TCScheFBack;
> +    uint32_t ISAMode; /* MIPS32 or MIPS16 mode */
>      int32_t CP0_Debug_tcstatus;
>  };

I am fine with this.

> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index e9d9224..b0a1b29 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -463,6 +463,7 @@ typedef struct DisasContext {
>      struct TranslationBlock *tb;
>      target_ulong pc, saved_pc;
>      uint32_t opcode;
> +    int isa_mode;
>      int singlestep_enabled;
>      /* Routine used to access memory */
>      int mem_idx;
> @@ -8306,6 +8307,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
>      ctx.pc = pc_start;
>      ctx.saved_pc = -1;
>      ctx.singlestep_enabled = env->singlestep_enabled;
> +    ctx.isa_mode = env->active_tc.ISAMode;
>      ctx.tb = tb;
>      ctx.bstate = BS_NONE;
>      /* Restore delay slot state from the tb context.  */

Instead of a new ctx value, it's probably better to use a new bit in
hflags. It is also necessary to change MIPS_HFLAG_TMASK accordingly, to
ensure a MIPS16 translation block is not later executed while ISAMode is
0 (while it should generate an exception) and vice-versa.

This also mean that hflags should be recomputed each time ISAMode is
changed.

On Sat, Nov 28, 2009 at 11:17:20AM +0100, Aurelien Jarno wrote:
> On Mon, Nov 23, 2009 at 12:49:59PM -0800, Nathan Froyd wrote:
> > 
> > Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> > ---
> >  target-mips/cpu.h       |    1 +
> >  target-mips/translate.c |    2 ++
> >  2 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> > index 82f9a38..e8febe6 100644
> > --- a/target-mips/cpu.h
> > +++ b/target-mips/cpu.h
> > @@ -167,6 +167,7 @@ struct TCState {
> >      target_ulong CP0_TCContext;
> >      target_ulong CP0_TCSchedule;
> >      target_ulong CP0_TCScheFBack;
> > +    uint32_t ISAMode; /* MIPS32 or MIPS16 mode */
> >      int32_t CP0_Debug_tcstatus;
> >  };
> 
> I am fine with this.
> 
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index e9d9224..b0a1b29 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -463,6 +463,7 @@ typedef struct DisasContext {
> >      struct TranslationBlock *tb;
> >      target_ulong pc, saved_pc;
> >      uint32_t opcode;
> > +    int isa_mode;
> >      int singlestep_enabled;
> >      /* Routine used to access memory */
> >      int mem_idx;
> > @@ -8306,6 +8307,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
> >      ctx.pc = pc_start;
> >      ctx.saved_pc = -1;
> >      ctx.singlestep_enabled = env->singlestep_enabled;
> > +    ctx.isa_mode = env->active_tc.ISAMode;
> >      ctx.tb = tb;
> >      ctx.bstate = BS_NONE;
> >      /* Restore delay slot state from the tb context.  */
> 
> Instead of a new ctx value, it's probably better to use a new bit in
> hflags. It is also necessary to change MIPS_HFLAG_TMASK accordingly, to
> ensure a MIPS16 translation block is not later executed while ISAMode is
> 0 (while it should generate an exception) and vice-versa.
> 
> This also mean that hflags should be recomputed each time ISAMode is
> changed.
> 

Actually just changing ctx.hflags is enough, as it is automatically
saved to env->hflags at the end of the TB or if an exception can occur.