Message ID | 20091125170415.5446.15073.sendpatchset@localhost |
---|---|
State | Not Applicable |
Delegated to: | David Miller |
Headers | show |
On Wed, 25 Nov 2009 18:04:15 +0100 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: > From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> > Subject: [PATCH] pata_efar: MWDMA0 is unsupported > > MWDMA0 timings cannot be met with the PIIX based controller > programming interface. The efar documentation makes no reference to not being capable of MWDMA0, so where does this come from ? No MWDMA0 is an Intel erratum it appears. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote: > On Wed, 25 Nov 2009 18:04:15 +0100 > Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: > > > From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> > > Subject: [PATCH] pata_efar: MWDMA0 is unsupported > > > > MWDMA0 timings cannot be met with the PIIX based controller > > programming interface. > > The efar documentation makes no reference to not being capable of MWDMA0, > so where does this come from ? No MWDMA0 is an Intel erratum it appears. No MWDMA0 support is a common issue on all 'PIIX-like' controllers. In case of this chipset while the (preliminary) documentation claims MWDMA0 support on the 'FEATURES' page the later 'programming guide' part describes only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. -- Bartlomiej Zolnierkiewicz -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, 26 Nov 2009 15:53:58 +0100 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: > On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote: > > On Wed, 25 Nov 2009 18:04:15 +0100 > > Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: > > > > > From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> > > > Subject: [PATCH] pata_efar: MWDMA0 is unsupported > > > > > > MWDMA0 timings cannot be met with the PIIX based controller > > > programming interface. > > > > The efar documentation makes no reference to not being capable of MWDMA0, > > so where does this come from ? No MWDMA0 is an Intel erratum it appears. > > No MWDMA0 support is a common issue on all 'PIIX-like' controllers. > > In case of this chipset while the (preliminary) documentation claims MWDMA0 > support on the 'FEATURES' page the later 'programming guide' part describes > only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. Cool - I only have the original docs. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. Alan Cox wrote: >>On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote: >>>On Wed, 25 Nov 2009 18:04:15 +0100 >>>Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: >>>>From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> >>>>Subject: [PATCH] pata_efar: MWDMA0 is unsupported >>>>MWDMA0 timings cannot be met with the PIIX based controller >>>>programming interface. >>>The efar documentation makes no reference to not being capable of MWDMA0, >>>so where does this come from ? No MWDMA0 is an Intel erratum it appears. >>No MWDMA0 support is a common issue on all 'PIIX-like' controllers. >>In case of this chipset while the (preliminary) documentation claims MWDMA0 >>support on the 'FEATURES' page the later 'programming guide' part describes >>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. > Cool - I only have the original docs. Hm, me too... perhaps worth putting in Jeff's documentation archive? MBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thursday 26 November 2009 04:33:13 pm Sergei Shtylyov wrote: > Hello. > > Alan Cox wrote: > > >>On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote: > > >>>On Wed, 25 Nov 2009 18:04:15 +0100 > >>>Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote: > > >>>>From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> > >>>>Subject: [PATCH] pata_efar: MWDMA0 is unsupported > > >>>>MWDMA0 timings cannot be met with the PIIX based controller > >>>>programming interface. > > >>>The efar documentation makes no reference to not being capable of MWDMA0, > >>>so where does this come from ? No MWDMA0 is an Intel erratum it appears. > > >>No MWDMA0 support is a common issue on all 'PIIX-like' controllers. > > >>In case of this chipset while the (preliminary) documentation claims MWDMA0 > >>support on the 'FEATURES' page the later 'programming guide' part describes > >>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. > > > Cool - I only have the original docs. > > Hm, me too... perhaps worth putting in Jeff's documentation archive? Me too? I just have what 'The Good Uncle Google' has.. -- Bartlomiej Zolnierkiewicz -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello. Bartlomiej Zolnierkiewicz wrote: >>>>>>MWDMA0 timings cannot be met with the PIIX based controller >>>>>>programming interface. >>>>>The efar documentation makes no reference to not being capable of MWDMA0, >>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears. >>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers. >>>>In case of this chipset while the (preliminary) documentation claims MWDMA0 >>>>support on the 'FEATURES' page the later 'programming guide' part describes >>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. >>>Cool - I only have the original docs. >> Hm, me too... perhaps worth putting in Jeff's documentation archive? > Me too? I just have what 'The Good Uncle Google' has.. Well, I've googled for it and was unable to find any valid links even to my preliminary version anymore. Perhaps I haven't looked hard enough... > -- > Bartlomiej Zolnierkiewicz MBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thursday 26 November 2009 05:17:00 pm Sergei Shtylyov wrote: > Hello. > > Bartlomiej Zolnierkiewicz wrote: > > >>>>>>MWDMA0 timings cannot be met with the PIIX based controller > >>>>>>programming interface. > > >>>>>The efar documentation makes no reference to not being capable of MWDMA0, > >>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears. > > >>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers. > > >>>>In case of this chipset while the (preliminary) documentation claims MWDMA0 > >>>>support on the 'FEATURES' page the later 'programming guide' part describes > >>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. > > >>>Cool - I only have the original docs. > > >> Hm, me too... perhaps worth putting in Jeff's documentation archive? > > > Me too? I just have what 'The Good Uncle Google' has.. > > Well, I've googled for it and was unable to find any valid links even to > my preliminary version anymore. Perhaps I haven't looked hard enough... Maybe... ;) FWIW my file is called 38384_SMSC_SLC90E66.pdf -- Bartlomiej Zolnierkiewicz -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Bartlomiej Zolnierkiewicz wrote: >>>>>>>>MWDMA0 timings cannot be met with the PIIX based controller >>>>>>>>programming interface. >>>>>>>The efar documentation makes no reference to not being capable of MWDMA0, >>>>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears. >>>>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers. >>>>>>In case of this chipset while the (preliminary) documentation claims MWDMA0 >>>>>>support on the 'FEATURES' page the later 'programming guide' part describes >>>>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. >>>>>Cool - I only have the original docs. >>>> Hm, me too... perhaps worth putting in Jeff's documentation archive? >>>Me too? I just have what 'The Good Uncle Google' has.. >> Well, I've googled for it and was unable to find any valid links even to >>my preliminary version anymore. Perhaps I haven't looked hard enough... > Maybe... ;) > FWIW my file is called 38384_SMSC_SLC90E66.pdf Well, that brought me to some Chinese site with 07/10/2002 version (which I've already found minutes before that). But it still claims support for MWDMA0 under the features... ah, I need to look further down... no "programming guide" part, hm... but thanks anyway. :-) > -- > Bartlomiej Zolnierkiewicz WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 11/26/2009 10:15 AM, Alan Cox wrote: > On Thu, 26 Nov 2009 15:53:58 +0100 > Bartlomiej Zolnierkiewicz<bzolnier@gmail.com> wrote: > >> On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote: >>> On Wed, 25 Nov 2009 18:04:15 +0100 >>> Bartlomiej Zolnierkiewicz<bzolnier@gmail.com> wrote: >>> >>>> From: Bartlomiej Zolnierkiewicz<bzolnier@gmail.com> >>>> Subject: [PATCH] pata_efar: MWDMA0 is unsupported >>>> >>>> MWDMA0 timings cannot be met with the PIIX based controller >>>> programming interface. >>> >>> The efar documentation makes no reference to not being capable of MWDMA0, >>> so where does this come from ? No MWDMA0 is an Intel erratum it appears. >> >> No MWDMA0 support is a common issue on all 'PIIX-like' controllers. >> >> In case of this chipset while the (preliminary) documentation claims MWDMA0 >> support on the 'FEATURES' page the later 'programming guide' part describes >> only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported. > > Cool - I only have the original docs. ACK Bart's patch, then? This thread was a bit unclear, and I want to be certain (well, as certain as we can be :)) Jeff -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Index: b/drivers/ata/pata_efar.c =================================================================== --- a/drivers/ata/pata_efar.c +++ b/drivers/ata/pata_efar.c @@ -252,7 +252,7 @@ static int efar_init_one (struct pci_dev static const struct ata_port_info info = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, - .mwdma_mask = ATA_MWDMA2, + .mwdma_mask = ATA_MWDMA12_ONLY, .udma_mask = ATA_UDMA4, .port_ops = &efar_ops, };