diff mbox

[16/86] pata_efar: MWDMA0 is unsupported

Message ID 20091125170415.5446.15073.sendpatchset@localhost
State Not Applicable
Delegated to: David Miller
Headers show

Commit Message

Bartlomiej Zolnierkiewicz Nov. 25, 2009, 5:04 p.m. UTC 
From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Subject: [PATCH] pata_efar: MWDMA0 is unsupported

MWDMA0 timings cannot be met with the PIIX based controller
programming interface.

This change should be safe as this is how we have been doing
things in IDE slc90e66 host driver for years.

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
---
 drivers/ata/pata_efar.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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Comments

Alan Cox Nov. 25, 2009, 5:25 p.m. UTC | #1 
On Wed, 25 Nov 2009 18:04:15 +0100
Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:

> From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> Subject: [PATCH] pata_efar: MWDMA0 is unsupported
> 
> MWDMA0 timings cannot be met with the PIIX based controller
> programming interface.

The efar documentation makes no reference to not being capable of MWDMA0,
so where does this come from ? No MWDMA0 is an Intel erratum it appears.
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Bartlomiej Zolnierkiewicz Nov. 26, 2009, 2:53 p.m. UTC | #2 
On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote:
> On Wed, 25 Nov 2009 18:04:15 +0100
> Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:
> 
> > From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> > Subject: [PATCH] pata_efar: MWDMA0 is unsupported
> > 
> > MWDMA0 timings cannot be met with the PIIX based controller
> > programming interface.
> 
> The efar documentation makes no reference to not being capable of MWDMA0,
> so where does this come from ? No MWDMA0 is an Intel erratum it appears.

No MWDMA0 support is a common issue on all 'PIIX-like' controllers.

In case of this chipset while the (preliminary) documentation claims MWDMA0
support on the 'FEATURES' page the later 'programming guide' part describes
only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.

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Bartlomiej Zolnierkiewicz
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Alan Cox Nov. 26, 2009, 3:15 p.m. UTC | #3 
On Thu, 26 Nov 2009 15:53:58 +0100
Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:

> On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote:
> > On Wed, 25 Nov 2009 18:04:15 +0100
> > Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:
> > 
> > > From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> > > Subject: [PATCH] pata_efar: MWDMA0 is unsupported
> > > 
> > > MWDMA0 timings cannot be met with the PIIX based controller
> > > programming interface.
> > 
> > The efar documentation makes no reference to not being capable of MWDMA0,
> > so where does this come from ? No MWDMA0 is an Intel erratum it appears.
> 
> No MWDMA0 support is a common issue on all 'PIIX-like' controllers.
> 
> In case of this chipset while the (preliminary) documentation claims MWDMA0
> support on the 'FEATURES' page the later 'programming guide' part describes
> only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.

Cool - I only have the original docs.
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Sergei Shtylyov Nov. 26, 2009, 3:33 p.m. UTC | #4 
Hello.

Alan Cox wrote:

>>On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote:

>>>On Wed, 25 Nov 2009 18:04:15 +0100
>>>Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:

>>>>From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
>>>>Subject: [PATCH] pata_efar: MWDMA0 is unsupported

>>>>MWDMA0 timings cannot be met with the PIIX based controller
>>>>programming interface.

>>>The efar documentation makes no reference to not being capable of MWDMA0,
>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears.

>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers.

>>In case of this chipset while the (preliminary) documentation claims MWDMA0
>>support on the 'FEATURES' page the later 'programming guide' part describes
>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.

> Cool - I only have the original docs.

    Hm, me too... perhaps worth putting in Jeff's documentation archive?

MBR, Sergei
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Bartlomiej Zolnierkiewicz Nov. 26, 2009, 3:40 p.m. UTC | #5 
On Thursday 26 November 2009 04:33:13 pm Sergei Shtylyov wrote:
> Hello.
> 
> Alan Cox wrote:
> 
> >>On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote:
> 
> >>>On Wed, 25 Nov 2009 18:04:15 +0100
> >>>Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> wrote:
> 
> >>>>From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> >>>>Subject: [PATCH] pata_efar: MWDMA0 is unsupported
> 
> >>>>MWDMA0 timings cannot be met with the PIIX based controller
> >>>>programming interface.
> 
> >>>The efar documentation makes no reference to not being capable of MWDMA0,
> >>>so where does this come from ? No MWDMA0 is an Intel erratum it appears.
> 
> >>No MWDMA0 support is a common issue on all 'PIIX-like' controllers.
> 
> >>In case of this chipset while the (preliminary) documentation claims MWDMA0
> >>support on the 'FEATURES' page the later 'programming guide' part describes
> >>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.
> 
> > Cool - I only have the original docs.
> 
>     Hm, me too... perhaps worth putting in Jeff's documentation archive?

Me too?  I just have what 'The Good Uncle Google' has..

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Sergei Shtylyov Nov. 26, 2009, 4:17 p.m. UTC | #6 
Hello.

Bartlomiej Zolnierkiewicz wrote:

>>>>>>MWDMA0 timings cannot be met with the PIIX based controller
>>>>>>programming interface.

>>>>>The efar documentation makes no reference to not being capable of MWDMA0,
>>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears.

>>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers.

>>>>In case of this chipset while the (preliminary) documentation claims MWDMA0
>>>>support on the 'FEATURES' page the later 'programming guide' part describes
>>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.

>>>Cool - I only have the original docs.

>>    Hm, me too... perhaps worth putting in Jeff's documentation archive?

> Me too?  I just have what 'The Good Uncle Google' has..

    Well, I've googled for it and was unable to find any valid links even to 
my preliminary version anymore. Perhaps I haven't looked hard enough...

> --
> Bartlomiej Zolnierkiewicz

MBR, Sergei
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Bartlomiej Zolnierkiewicz Nov. 26, 2009, 4:29 p.m. UTC | #7 
On Thursday 26 November 2009 05:17:00 pm Sergei Shtylyov wrote:
> Hello.
> 
> Bartlomiej Zolnierkiewicz wrote:
> 
> >>>>>>MWDMA0 timings cannot be met with the PIIX based controller
> >>>>>>programming interface.
> 
> >>>>>The efar documentation makes no reference to not being capable of MWDMA0,
> >>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears.
> 
> >>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers.
> 
> >>>>In case of this chipset while the (preliminary) documentation claims MWDMA0
> >>>>support on the 'FEATURES' page the later 'programming guide' part describes
> >>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.
> 
> >>>Cool - I only have the original docs.
> 
> >>    Hm, me too... perhaps worth putting in Jeff's documentation archive?
> 
> > Me too?  I just have what 'The Good Uncle Google' has..
> 
>     Well, I've googled for it and was unable to find any valid links even to 
> my preliminary version anymore. Perhaps I haven't looked hard enough...

Maybe... ;)

FWIW my file is called 38384_SMSC_SLC90E66.pdf

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Sergei Shtylyov Nov. 26, 2009, 4:44 p.m. UTC | #8 
Bartlomiej Zolnierkiewicz wrote:

>>>>>>>>MWDMA0 timings cannot be met with the PIIX based controller
>>>>>>>>programming interface.

>>>>>>>The efar documentation makes no reference to not being capable of MWDMA0,
>>>>>>>so where does this come from ? No MWDMA0 is an Intel erratum it appears.

>>>>>>No MWDMA0 support is a common issue on all 'PIIX-like' controllers.

>>>>>>In case of this chipset while the (preliminary) documentation claims MWDMA0
>>>>>>support on the 'FEATURES' page the later 'programming guide' part describes
>>>>>>only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.

>>>>>Cool - I only have the original docs.

>>>>   Hm, me too... perhaps worth putting in Jeff's documentation archive?

>>>Me too?  I just have what 'The Good Uncle Google' has..

>>    Well, I've googled for it and was unable to find any valid links even to 
>>my preliminary version anymore. Perhaps I haven't looked hard enough...

> Maybe... ;)

> FWIW my file is called 38384_SMSC_SLC90E66.pdf

    Well, that brought me to some Chinese site with 07/10/2002 version 
(which I've already found minutes before that). But it still claims support 
for MWDMA0 under the features... ah, I need to look further down... no 
"programming guide" part, hm... but thanks anyway. :-)

> --
> Bartlomiej Zolnierkiewicz

WBR, Sergei
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Jeff Garzik Dec. 3, 2009, 8:50 p.m. UTC | #9 
On 11/26/2009 10:15 AM, Alan Cox wrote:
> On Thu, 26 Nov 2009 15:53:58 +0100
> Bartlomiej Zolnierkiewicz<bzolnier@gmail.com>  wrote:
>
>> On Wednesday 25 November 2009 06:25:52 pm Alan Cox wrote:
>>> On Wed, 25 Nov 2009 18:04:15 +0100
>>> Bartlomiej Zolnierkiewicz<bzolnier@gmail.com>  wrote:
>>>
>>>> From: Bartlomiej Zolnierkiewicz<bzolnier@gmail.com>
>>>> Subject: [PATCH] pata_efar: MWDMA0 is unsupported
>>>>
>>>> MWDMA0 timings cannot be met with the PIIX based controller
>>>> programming interface.
>>>
>>> The efar documentation makes no reference to not being capable of MWDMA0,
>>> so where does this come from ? No MWDMA0 is an Intel erratum it appears.
>>
>> No MWDMA0 support is a common issue on all 'PIIX-like' controllers.
>>
>> In case of this chipset while the (preliminary) documentation claims MWDMA0
>> support on the 'FEATURES' page the later 'programming guide' part describes
>> only PIO0-4, SWDMA2, MWDMA1-2 and UDMA0-4 transfer modes as supported.
>
> Cool - I only have the original docs.

ACK Bart's patch, then?

This thread was a bit unclear, and I want to be certain (well, as 
certain as we can be :))

	Jeff



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diff mbox

Patch

Index: b/drivers/ata/pata_efar.c
===================================================================
--- a/drivers/ata/pata_efar.c
+++ b/drivers/ata/pata_efar.c
@@ -252,7 +252,7 @@  static int efar_init_one (struct pci_dev
 	static const struct ata_port_info info = {
 		.flags		= ATA_FLAG_SLAVE_POSS,
 		.pio_mask	= ATA_PIO4,
-		.mwdma_mask	= ATA_MWDMA2,
+		.mwdma_mask	= ATA_MWDMA12_ONLY,
 		.udma_mask 	= ATA_UDMA4,
 		.port_ops	= &efar_ops,
 	};