| Message ID | 1413753085-9958-10-git-send-email-christophe-h.ricard@st.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
Hi, can I get an ACK from the device tree gurus? Am Sonntag, 19. Oktober 2014, 23:11:19 schrieb Christophe Ricard: > st33zp24 tpm can be seen as a trivial i2c device as other i2c tpm. > However several other properties needs to be documented such as lpcpd. > > Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> > Signed-off-by: Christophe Ricard <christophe-h.ricard@st.com> > --- > .../devicetree/bindings/security/tpm/st33zp24.txt | 36 > ++++++++++++++++++++++ 1 file changed, 36 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/security/tpm/st33zp24.txt > > diff --git a/Documentation/devicetree/bindings/security/tpm/st33zp24.txt > b/Documentation/devicetree/bindings/security/tpm/st33zp24.txt new file > mode 100644 > index 0000000..eb48222 > --- /dev/null > +++ b/Documentation/devicetree/bindings/security/tpm/st33zp24.txt > @@ -0,0 +1,36 @@ > +* STMicroelectronics SAS. ST33ZP24 TPM SoC > + > +Required properties: > +- compatible: Should be "st,st33zp24_i2c". > +- clock-frequency: I²C work frequency. > +- reg: address on the bus > + > +Optional ST33ZP24 Properties: > +- interrupt-parent: phandle for the interrupt gpio controller > +- interrupts: GPIO interrupt to which the chip is connected > +- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 > state. +If set vps must present when the platform is going into > sleep/hibernate mode. + > +Optional SoC Specific Properties: > +- pinctrl-names: Contains only one value - "default". > +- pintctrl-0: Specifies the pin control groups used for this controller. > + > +Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2): > + > +&i2c2 { > + > + status = "okay"; > + > + st33zp24: st33zp24@13 { > + > + compatible = "st,st33zp24_i2c"; > + > + reg = <0x013>; > + clock-frequency = <400000>; > + > + interrupt-parent = <&gpio5>; > + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; > + > + lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; > + }; > +}; Thanks, Peter ------------------------------------------------------------------------------ Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server from Actuate! Instantly Supercharge Your Business Reports and Dashboards with Interactivity, Sharing, Native Excel Exports, App Integration & more Get technology previously reserved for billion-dollar corporations, FREE http://pubads.g.doubleclick.net/gampad/clk?id=157005751&iu=/4140/ostg.clktrk
diff --git a/Documentation/devicetree/bindings/security/tpm/st33zp24.txt b/Documentation/devicetree/bindings/security/tpm/st33zp24.txt new file mode 100644 index 0000000..eb48222 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/st33zp24.txt @@ -0,0 +1,36 @@ +* STMicroelectronics SAS. ST33ZP24 TPM SoC + +Required properties: +- compatible: Should be "st,st33zp24_i2c". +- clock-frequency: I²C work frequency. +- reg: address on the bus + +Optional ST33ZP24 Properties: +- interrupt-parent: phandle for the interrupt gpio controller +- interrupts: GPIO interrupt to which the chip is connected +- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state. +If set vps must present when the platform is going into sleep/hibernate mode. + +Optional SoC Specific Properties: +- pinctrl-names: Contains only one value - "default". +- pintctrl-0: Specifies the pin control groups used for this controller. + +Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2): + +&i2c2 { + + status = "okay"; + + st33zp24: st33zp24@13 { + + compatible = "st,st33zp24_i2c"; + + reg = <0x013>; + clock-frequency = <400000>; + + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + + lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + }; +};