| Message ID | 1417073716-22997-3-git-send-email-cw00.choi@samsung.com |
|---|---|
| State | Needs Review / ACK, archived |
| Headers | show |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 1 errors, 0 warnings, 0 lines checked |
| robh/patch-applied | success |
On Thu, Nov 27, 2014 at 07:34:59AM +0000, Chanwoo Choi wrote: > This patch add binding documentation for Exynos5433 clock controller. > Exynos5433 has various clock domains So, this documentation explains > the detailed clock domains ans usage guide. > > Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > Acked-by: Inki Dae <inki.dae@samsung.com> > Acked-by: Geunsik Lim <geunsik.lim@samsung.com> > --- > .../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++++++++++++++++++++ > 1 file changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt > > diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > new file mode 100644 > index 0000000..72cd0ba > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt > @@ -0,0 +1,106 @@ > +* Samsung Exynos5433 CMU (Clock Management Units) > + > +The Exynos5433 clock controller generates and supplies clock to various > +controllers within the Exynos5433 SoC. > + > +Required Properties: > + > +- compatible: should be one of the following. > + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP > + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS > + domains and bus clocks. > + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF > + which generates clocks for LLI (Low Latency Interface) IP. > + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF > + which generates clocks for DRAM Memory Controller domain. > + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC > + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. > + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS > + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. > + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS > + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. > + > +- reg: physical base address of the controller and length of memory mapped > + region. > + > +- #clock-cells: should be 1. > + > +Each clock is assigned an identifier and client nodes can use this identifier > +to specify the clock which they consume. > + > +All available clocks are defined as preprocessor macros in > +dt-bindings/clock/exynos5433.h header and can be used in device > +tree sources. That header should be added as part of this patch, otehrwise this is incomplete. Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Dear Mark, On 11/27/2014 08:21 PM, Mark Rutland wrote: > On Thu, Nov 27, 2014 at 07:34:59AM +0000, Chanwoo Choi wrote: >> This patch add binding documentation for Exynos5433 clock controller. >> Exynos5433 has various clock domains So, this documentation explains >> the detailed clock domains ans usage guide. >> >> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> >> Cc: Tomasz Figa <tomasz.figa@gmail.com> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> Acked-by: Inki Dae <inki.dae@samsung.com> >> Acked-by: Geunsik Lim <geunsik.lim@samsung.com> >> --- >> .../devicetree/bindings/clock/exynos5433-clock.txt | 106 +++++++++++++++++++++ >> 1 file changed, 106 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> new file mode 100644 >> index 0000000..72cd0ba >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt >> @@ -0,0 +1,106 @@ >> +* Samsung Exynos5433 CMU (Clock Management Units) >> + >> +The Exynos5433 clock controller generates and supplies clock to various >> +controllers within the Exynos5433 SoC. >> + >> +Required Properties: >> + >> +- compatible: should be one of the following. >> + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP >> + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS >> + domains and bus clocks. >> + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF >> + which generates clocks for LLI (Low Latency Interface) IP. >> + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF >> + which generates clocks for DRAM Memory Controller domain. >> + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC >> + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. >> + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS >> + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. >> + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS >> + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. >> + >> +- reg: physical base address of the controller and length of memory mapped >> + region. >> + >> +- #clock-cells: should be 1. >> + >> +Each clock is assigned an identifier and client nodes can use this identifier >> +to specify the clock which they consume. >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/exynos5433.h header and can be used in device >> +tree sources. > > That header should be added as part of this patch, otehrwise this is > incomplete. OK, I'll merge two patches (patch2 and patch3) by solving this issue. patch2 : [PATCH 02/19] clk: samsung: Add binding documentation for Exynos5433 clock controller patch3 : [PATCH 03/19] clk: samsung: exynos5433: Add clocks using common clock framework Thanks for your review. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt new file mode 100644 index 0000000..72cd0ba --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt @@ -0,0 +1,106 @@ +* Samsung Exynos5433 CMU (Clock Management Units) + +The Exynos5433 clock controller generates and supplies clock to various +controllers within the Exynos5433 SoC. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP + which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS + domains and bus clocks. + - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF + which generates clocks for LLI (Low Latency Interface) IP. + - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF + which generates clocks for DRAM Memory Controller domain. + - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC + which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. + - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS + which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. + - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS + which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos5433.h header and can be used in device +tree sources. + +Example 1: Examples of clock controller nodes are listed below. + + cmu_top: clock-controller@0x10030000 { + compatible = "samsung,exynos5433-cmu-top"; + reg = <0x10030000 0x0c04>; + #clock-cells = <1>; + }; + + cmu_cpif: clock-controller@0x10fc0000 { + compatible = "samsung,exynos5433-cmu-cpif"; + reg = <0x10fc0000 0x0c04>; + #clock-cells = <1>; + }; + + cmu_mif: clock-controller@0x105b0000 { + compatible = "samsung,exynos5433-cmu-mif"; + reg = <0x105b0000 0x100c>; + #clock-cells = <1>; + }; + + cmu_peric: clock-controller@0x14c80000 { + compatible = "samsung,exynos5433-cmu-peric"; + reg = <0x14c80000 0x0b08>; + #clock-cells = <1>; + }; + + cmu_peris: clock-controller@0x10040000 { + compatible = "samsung,exynos5433-cmu-peris"; + reg = <0x10040000 0x0b20>; + #clock-cells = <1>; + }; + + cmu_fsys: clock-controller@0x156e0000 { + compatible = "samsung,exynos5433-cmu-fsys"; + reg = <0x156e0000 0x0b04>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. + + serial_0: serial@14C10000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x14C10000 0x100>; + interrupts = <0 421 0>; + clocks = <&cmu_peric CLK_PCLK_UART0>, + <&cmu_peric CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + status = "disabled"; + }; + +Example 3: SPI controller node that consumes the clock generated by the clock + controller. + + spi_0: spi@14d20000 { + compatible = "samsung,exynos7-spi"; + reg = <0x14d20000 0x100>; + interrupts = <0 432 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric CLK_PCLK_SPI0>, + <&cmu_top CLK_SCLK_SPI0_PERIC>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + };