| Message ID | 20090818233818.GA29042@oksana.dev.rtsoft.ru (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | ec80fb2d89a0a93db46bdc968b6a849be5340531 |
| Delegated to: | Kumar Gala |
| Headers | show |
On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > This patch simply adds sdhci node to the device tree. > > We specify clock-frequency manually, so that eSDHC will work without > upgrading U-Boot. Though, that'll only work for default setup (1500 > MHz) on new board revisions. For non-default setups, it's recommended > to upgrade U-Boot, since it will fixup clock-frequency automatically. > > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> out of interest the 85xx eSDHC don't need the sdhci,wp-inverted property? - k
On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote: > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > > >This patch simply adds sdhci node to the device tree. > > > >We specify clock-frequency manually, so that eSDHC will work without > >upgrading U-Boot. Though, that'll only work for default setup (1500 > >MHz) on new board revisions. For non-default setups, it's recommended > >to upgrade U-Boot, since it will fixup clock-frequency automatically. > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted > property? Yes, eSDHC controllers in MPC85xx report normal state in its registers. But the funny thing is that the switch itself is inverted, so to enable writing, on MPC8569E-MDS and MPC8536DS boards we have to place card's write protect tab into "lock" position. Unfortunately we can't fix that in software since controller doesn't permit write operations if it detects write-protected state. On the bright side, IIRC MPC8536DS revision history says that WP line level is fixed via BCSR upgrade. Not sure if it is possible to fix it for MPC8569E-MDS.
On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > This patch simply adds sdhci node to the device tree. > > We specify clock-frequency manually, so that eSDHC will work without > upgrading U-Boot. Though, that'll only work for default setup (1500 > MHz) on new board revisions. For non-default setups, it's recommended > to upgrade U-Boot, since it will fixup clock-frequency automatically. > > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > --- > > On Tue, Aug 11, 2009 at 08:48:32AM -0500, Kumar Gala wrote: >> On Aug 7, 2009, at 2:58 PM, Anton Vorontsov wrote: >>> This patch simply adds sdhci node to the device tree. >>> >>> We specify clock-frequency manually, so that eSDHC will work without >>> upgrading U-Boot. Though, that'll only work for default setup (1500 >>> MHz) on new board revisions. For non-default setups, it's >>> recommended >>> to upgrade U-Boot, since it will fixup clock-frequency >>> automatically. >>> >>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> >>> --- >>> arch/powerpc/boot/dts/mpc8536ds.dts | 8 ++++++++ >>> 1 files changed, 8 insertions(+), 0 deletions(-) >> >> Can you update the mpc8536ds_36b.dts as well (its in my next branch) > > Sure thing. > > arch/powerpc/boot/dts/mpc8536ds.dts | 8 ++++++++ > arch/powerpc/boot/dts/mpc8536ds_36b.dts | 8 ++++++++ > 2 files changed, 16 insertions(+), 0 deletions(-) applied to next. - k
> -----Original Message----- > From: > linuxppc-dev-bounces+b21284=freescale.com@lists.ozlabs.org > [mailto:linuxppc-dev-bounces+b21284=freescale.com@lists.ozlabs > .org] On Behalf Of Anton Vorontsov > Sent: Wednesday, August 19, 2009 9:51 AM > To: Kumar Gala > Cc: Ben Dooks; linux-kernel@vger.kernel.org; > sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew > Morton; Pierre Ossman; David Vrabel > Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for > MPC8536DS boards > > On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote: > > > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > > > > >This patch simply adds sdhci node to the device tree. > > > > > >We specify clock-frequency manually, so that eSDHC will > work without > > >upgrading U-Boot. Though, that'll only work for default setup (1500 > > >MHz) on new board revisions. For non-default setups, it's > recommended > > >to upgrade U-Boot, since it will fixup clock-frequency > automatically. > > > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted > > property? > > Yes, eSDHC controllers in MPC85xx report normal state in its > registers. > Hi Anton, The eSDHC controller in different silicon version on MPC8536 reports different WP state in the register PRSSTAT: Silicon 1.0: Card WP pos PRSSTAT[WPSPL] RMMCR[SDHC_WP] GENCFG[SDHC_WP_INV] ------------------------------------------------------------------------ --------------------------------------------- unLock 1 1 / Lock 0 1 / Silicon 1.1: Card WP pos PRSSTAT[WPSPL] RMMCR[SDHC_WP] GENCFG[SDHC_WP_INV] ------------------------------------------------------------------------ --------------------------------------------- unLock 0 1 0 Lock 1 1 0 Note: the register GENCFG is added on silicon 1.1 to invert the WP state. For silicon 1.0, the macro SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also defined, so the dirver will report the error WP state in function sdhci_get_ro. Best regards, Mingkai
On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote: > > On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote: > > > > > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > > > > > > >This patch simply adds sdhci node to the device tree. > > > > > > > >We specify clock-frequency manually, so that eSDHC will > > work without > > > >upgrading U-Boot. Though, that'll only work for default setup (1500 > > > >MHz) on new board revisions. For non-default setups, it's > > recommended > > > >to upgrade U-Boot, since it will fixup clock-frequency > > automatically. > > > > > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > > > > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted > > > property? > > > > Yes, eSDHC controllers in MPC85xx report normal state in its > > registers. > > > > Hi Anton, > > The eSDHC controller in different silicon version on MPC8536 reports > different WP state in the register PRSSTAT: Thanks a million for the heads up! Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't mention that, but the newer manual that I just downloaded ("MPC8536ERM Rev. 1 05/2009") does. [...] > For silicon 1.0, the macro SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also > defined, > so the dirver will report the error WP state in function sdhci_get_ro. Not any longer. We don't actually define it for any 85xx CPUs. I need to think how should we handle all these WP inversions. :-) So, we have inversion in BCSR (depending on the BCSR revision), configurable inversion in CPU via GENCFGR for 1.1 silicon, and non-configurable non-inverted reporting for 1.0 silicon... Do you know if there are any plans to fix the WP inversion for MPC8569E-MDS boards, or make something like GENCFGR for MPC8569 CPUs? Thanks,
> -----Original Message----- > From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com] > Sent: Friday, August 28, 2009 11:20 PM > To: Hu Mingkai-B21284 > Cc: Kumar Gala; Ben Dooks; linux-kernel@vger.kernel.org; > sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew > Morton; Pierre Ossman; David Vrabel > Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for > MPC8536DS boards > > On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote: > > > On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote: > > > > > > > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote: > > > > > > > > >This patch simply adds sdhci node to the device tree. > > > > > > > > > >We specify clock-frequency manually, so that eSDHC will > > > work without > > > > >upgrading U-Boot. Though, that'll only work for default setup > > > > >(1500 > > > > >MHz) on new board revisions. For non-default setups, it's > > > recommended > > > > >to upgrade U-Boot, since it will fixup clock-frequency > > > automatically. > > > > > > > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > > > > > > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted > > > > property? > > > > > > Yes, eSDHC controllers in MPC85xx report normal state in its > > > registers. > > > > > > > Hi Anton, > > > > The eSDHC controller in different silicon version on > MPC8536 reports > > different WP state in the register PRSSTAT: > > Thanks a million for the heads up! > > Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't > mention that, but the newer manual that I just downloaded > ("MPC8536ERM Rev. 1 > 05/2009") does. > > [...] > > For silicon 1.0, the macro > SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also > > defined, so the dirver will report the error WP state in function > > sdhci_get_ro. > > Not any longer. We don't actually define it for any 85xx CPUs. > > I need to think how should we handle all these WP inversions. :-) > > So, we have inversion in BCSR (depending on the BCSR > revision), configurable inversion in CPU via GENCFGR for 1.1 > silicon, and non-configurable non-inverted reporting for 1.0 > silicon... > > Do you know if there are any plans to fix the WP inversion > for MPC8569E-MDS boards, or make something like GENCFGR for > MPC8569 CPUs? > > Thanks, > Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info, I'll inform you ASAP. :-) Best regards, Mingkai > -- > Anton Vorontsov > email: cbouatmailru@gmail.com > irc://irc.freenode.net/bd2 > >
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts index 22caf69..815cebb 100644 --- a/arch/powerpc/boot/dts/mpc8536ds.dts +++ b/arch/powerpc/boot/dts/mpc8536ds.dts @@ -250,6 +250,14 @@ phy_type = "ulpi"; }; + sdhci@2e000 { + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + clock-frequency = <250000000>; + }; + serial0: serial@4500 { cell-index = <0>; device_type = "serial"; diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts index 113ed8b..d95b260 100644 --- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts +++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts @@ -250,6 +250,14 @@ phy_type = "ulpi"; }; + sdhci@2e000 { + compatible = "fsl,mpc8536-esdhc", "fsl,esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <72 0x2>; + interrupt-parent = <&mpic>; + clock-frequency = <250000000>; + }; + serial0: serial@4500 { cell-index = <0>; device_type = "serial";