[AArch64/ARM,3/3] Add execution tests of ARM TRN Intrinsics

Final patch in series, adds new tests of the ARM TRN Intrinsics, that also check
the execution results, reusing the test bodies introduced into AArch64 in the
first patch. (These tests subsume the autogenerated ones in
testsuite/gcc.target/arm/neon/ that only check assembler output.)

Tests use gcc.target/arm/simd/simd.exp from corresponding patch for ZIP
Intrinsics, will commit that first.

All tests passing on arm-none-eabi.

testsuite/ChangeLog:
2012-03-28  Alan Lawrence  <alan.lawrence@arm.com>
	
	* gcc.target/arm/simd/vtrnqf32_1.c: New file.
	* gcc.target/arm/simd/vtrnqp16_1.c: New file.
	* gcc.target/arm/simd/vtrnqp8_1.c: New file.
	* gcc.target/arm/simd/vtrnqs16_1.c: New file.
	* gcc.target/arm/simd/vtrnqs32_1.c: New file.
	* gcc.target/arm/simd/vtrnqs8_1.c: New file.
	* gcc.target/arm/simd/vtrnqu16_1.c: New file.
	* gcc.target/arm/simd/vtrnqu32_1.c: New file.
	* gcc.target/arm/simd/vtrnqu8_1.c: New file.
	* gcc.target/arm/simd/vtrnf32_1.c: New file.
	* gcc.target/arm/simd/vtrnp16_1.c: New file.
	* gcc.target/arm/simd/vtrnp8_1.c: New file.
	* gcc.target/arm/simd/vtrns16_1.c: New file.
	* gcc.target/arm/simd/vtrns32_1.c: New file.
	* gcc.target/arm/simd/vtrns8_1.c: New file.
	* gcc.target/arm/simd/vtrnu16_1.c: New file.
	* gcc.target/arm/simd/vtrnu32_1.c: New file.
	* gcc.target/arm/simd/vtrnu8_1.c: New file.

On Fri, Mar 28, 2014 at 3:50 PM, Alan Lawrence <alan.lawrence@arm.com> wrote:
> Final patch in series, adds new tests of the ARM TRN Intrinsics, that also
> check
> the execution results, reusing the test bodies introduced into AArch64 in
> the
> first patch. (These tests subsume the autogenerated ones in
> testsuite/gcc.target/arm/neon/ that only check assembler output.)
>
> Tests use gcc.target/arm/simd/simd.exp from corresponding patch for ZIP
> Intrinsics, will commit that first.
>
> All tests passing on arm-none-eabi.

The ARM bits are ok.

>
> testsuite/ChangeLog:
> 2012-03-28  Alan Lawrence  <alan.lawrence@arm.com>
>
>         * gcc.target/arm/simd/vtrnqf32_1.c: New file.
>         * gcc.target/arm/simd/vtrnqp16_1.c: New file.
>         * gcc.target/arm/simd/vtrnqp8_1.c: New file.
>         * gcc.target/arm/simd/vtrnqs16_1.c: New file.
>         * gcc.target/arm/simd/vtrnqs32_1.c: New file.
>         * gcc.target/arm/simd/vtrnqs8_1.c: New file.
>         * gcc.target/arm/simd/vtrnqu16_1.c: New file.
>         * gcc.target/arm/simd/vtrnqu32_1.c: New file.
>         * gcc.target/arm/simd/vtrnqu8_1.c: New file.
>         * gcc.target/arm/simd/vtrnf32_1.c: New file.
>         * gcc.target/arm/simd/vtrnp16_1.c: New file.
>         * gcc.target/arm/simd/vtrnp8_1.c: New file.
>         * gcc.target/arm/simd/vtrns16_1.c: New file.
>         * gcc.target/arm/simd/vtrns32_1.c: New file.
>         * gcc.target/arm/simd/vtrns8_1.c: New file.
>         * gcc.target/arm/simd/vtrnu16_1.c: New file.
>         * gcc.target/arm/simd/vtrnu32_1.c: New file.
>         * gcc.target/arm/simd/vtrnu8_1.c: New file.
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
> new file mode 100644
> index 0000000..c9620fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnf32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnf32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
> new file mode 100644
> index 0000000..0ff4319
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnp16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnp16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
> new file mode 100644
> index 0000000..2b047e4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnp8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnp8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
> new file mode 100644
> index 0000000..dd4e883
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQf32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqf32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
> new file mode 100644
> index 0000000..374eee3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQp16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqp16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
> new file mode 100644
> index 0000000..b252fd5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQp8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqp8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
> new file mode 100644
> index 0000000..5f06d2a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQs16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqs16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
> new file mode 100644
> index 0000000..221175c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQs32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqs32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
> new file mode 100644
> index 0000000..9352b37
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQs8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqs8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
> new file mode 100644
> index 0000000..7f40109
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQu16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqu16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
> new file mode 100644
> index 0000000..1c61fc3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQu32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqu32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
> new file mode 100644
> index 0000000..82f911d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnQu8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnqu8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+,
> ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
> new file mode 100644
> index 0000000..af2c68f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrns16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrns16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
> new file mode 100644
> index 0000000..f5463a7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrns32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrns32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
> new file mode 100644
> index 0000000..395015d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrns8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrns8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
> new file mode 100644
> index 0000000..df0d963
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnu16' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnu16.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
> new file mode 100644
> index 0000000..95b6dec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnu32' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnu32.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
> b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
> new file mode 100644
> index 0000000..f5b4d68
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
> @@ -0,0 +1,12 @@
> +/* Test the `vtrnu8' ARM Neon intrinsic.  */
> +
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O1 -fno-inline" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +#include "../../aarch64/simd/vtrnu8.x"
> +
> +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+,
> ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
> +/* { dg-final { cleanup-saved-temps } } */