| Message ID | 1247781590-11323-1-git-send-email-nsnehaprabha@ti.com |
|---|---|
| State | New, archived |
| Headers | show |
nsnehaprabha@ti.com wrote: > +/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, > + * storing ten ECC bytes plus the manufacturer's bad block marker byte, > + * and not overlapping the default BBT markers. > + */ > +static struct nand_ecclayout hwecc4_2048 __initconst = { > + .eccbytes = 40, > + .eccpos = { > + /* at the end of spare sector */ > + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, > + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, > + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, > + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, > + }, > + .oobfree = { > + /* 1 byte at offset 0 holds manufacturer badblock marker */ > + {.offset = 1, .length = 23, }, > + /* 5 bytes at offset 8 hold BBT markers */ > + /* 8 bytes at offset 16 hold JFFS2 clean markers */ > + }, > +}; I hate to sound like a broken record, but If the bad block marker is only 1 byte. Don't you need to override static struct nand_bbt_descr largepage_flashbased = { .options = NAND_BBT_SCAN2NDPAGE, .offs = 0, .len = 2, .pattern = scan_ff_pattern }; I think it is easier just to leave it as 2 bytes. That may allow substituting a different manufacturers chip too.
> -----Original Message----- > From: Troy Kisky [mailto:troy.kisky@boundarydevices.com] > Sent: Thursday, July 16, 2009 7:57 PM > To: Narnakaje, Snehaprabha > Cc: linux-mtd@lists.infradead.org; davinci-linux-open- > source@linux.davincidsp.com; dwmw2@infradead.org; tglx@linutronix.de; > akpm@linux-foundation.org; Paulraj, Sandeep > Subject: Re: [PATCH v3 3/3] mtd-nand: DaVinci: Add 4-bit ECC support for > large page NAND chips > > nsnehaprabha@ti.com wrote: > > +/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, > > + * storing ten ECC bytes plus the manufacturer's bad block marker byte, > > + * and not overlapping the default BBT markers. > > + */ > > +static struct nand_ecclayout hwecc4_2048 __initconst = { > > + .eccbytes = 40, > > + .eccpos = { > > + /* at the end of spare sector */ > > + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, > > + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, > > + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, > > + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, > > + }, > > + .oobfree = { > > + /* 1 byte at offset 0 holds manufacturer badblock marker */ > > + {.offset = 1, .length = 23, }, > > + /* 5 bytes at offset 8 hold BBT markers */ > > + /* 8 bytes at offset 16 hold JFFS2 clean markers */ > > + }, > > +}; > > I hate to sound like a broken record, but > > If the bad block marker is only 1 byte. Don't you need to override > > static struct nand_bbt_descr largepage_flashbased = { > .options = NAND_BBT_SCAN2NDPAGE, > .offs = 0, > .len = 2, > .pattern = scan_ff_pattern > }; > > I think it is easier just to leave it as 2 bytes. That may > allow substituting a different manufacturers chip too. Yes, it is better to leave it as 2 bytes. Thanks Sneha > >
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 0fad648..14c72d2 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -348,6 +348,12 @@ compare: if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) return 0; + /* + * Clear any previous address calculation by doing a dummy read of an + * error address register. + */ + davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); + /* Start address calculation, and wait for it to complete. * We _could_ start reading more data while this is working, * to speed up the overall page read. @@ -359,8 +365,10 @@ compare: switch ((fsr >> 8) & 0x0f) { case 0: /* no error, should not happen */ + davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); return 0; case 1: /* five or more errors detected */ + davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); return -EIO; case 2: /* error addresses computed */ case 3: @@ -500,6 +508,26 @@ static struct nand_ecclayout hwecc4_small __initconst = { }, }; +/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, + * storing ten ECC bytes plus the manufacturer's bad block marker byte, + * and not overlapping the default BBT markers. + */ +static struct nand_ecclayout hwecc4_2048 __initconst = { + .eccbytes = 40, + .eccpos = { + /* at the end of spare sector */ + 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + /* 1 byte at offset 0 holds manufacturer badblock marker */ + {.offset = 1, .length = 23, }, + /* 5 bytes at offset 8 hold BBT markers */ + /* 8 bytes at offset 16 hold JFFS2 clean markers */ + }, +}; static int __init nand_davinci_probe(struct platform_device *pdev) { @@ -690,15 +718,20 @@ static int __init nand_davinci_probe(struct platform_device *pdev) info->mtd.oobsize - 16; goto syndrome_done; } + if (chunks == 4) { + info->ecclayout = hwecc4_2048; + info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; + goto syndrome_done; + } - /* For large page chips we'll be wanting to use a - * not-yet-implemented mode that reads OOB data - * before reading the body of the page, to avoid - * the "infix OOB" model of NAND_ECC_HW_SYNDROME - * (and preserve manufacturer badblock markings). + /* 4K page chips are not yet supported. The eccpos from + * nand_ecclayout cannot hold 80 bytes and change to eccpos[] + * breaks userspace ioctl interface with mtd-utils. Once we + * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used + * for the 4K page chips. */ dev_warn(&pdev->dev, "no 4-bit ECC support yet " - "for large page NAND\n"); + "for 4K page NAND\n"); ret = -EIO; goto err_scan;