| Message ID | 1390269732-22798-1-git-send-email-Yuantian.Tang@freescale.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Tue, 2014-01-21 at 10:02 +0800, Tang Yuantian wrote: > From: Tang Yuantian <yuantian.tang@freescale.com> > > Main changs include: > - Clarified the clock nodes' version number > - Fixed a issue in example > > Singed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> > --- > Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt > index 24711af..d6cadef 100644 > --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt > @@ -54,6 +54,8 @@ Required properties: > It takes parent's clock-frequency as its clock. > * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). > It takes parent's clock-frequency as its clock. > + Note: v1.0 and v2.0 are clock version which should align to > + clockgen node's they belong to which is chassis version. Instead, how about a note like this near the top of the file: All references to "1.0" and "2.0" refer to the QorIQ chassis version to which the chip complies. Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860, t1040 BTW, this binding and the associated driver really should be called "qoriq-clock", not "corenet-clock". This would match the compatible string, and it doesn't really have much to do with corenet (which is part of the QorIQ chassis v1 and v2, but not *this* part). Do you know if the chassis v3 clock interface will be similar enough to share a driver? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Wood Scott-B07421 > Sent: 2014年1月23日 星期四 8:44 > To: Tang Yuantian-B29983 > Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc- > dev@lists.ozlabs.org; devicetree@vger.kernel.org; Kushwaha Prabhakar- > B32579 > Subject: Re: [PATCH] clk: corenet: Update the clock bindings > > On Tue, 2014-01-21 at 10:02 +0800, Tang Yuantian wrote: > > From: Tang Yuantian <yuantian.tang@freescale.com> > > > > Main changs include: > > - Clarified the clock nodes' version number > > - Fixed a issue in example > > > > Singed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> > > --- > > Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt > > b/Documentation/devicetree/bindings/clock/corenet-clock.txt > > index 24711af..d6cadef 100644 > > --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt > > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt > > @@ -54,6 +54,8 @@ Required properties: > > It takes parent's clock-frequency as its clock. > > * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). > > It takes parent's clock-frequency as its clock. > > + Note: v1.0 and v2.0 are clock version which should align to > > + clockgen node's they belong to which is chassis version. > > Instead, how about a note like this near the top of the file: > > All references to "1.0" and "2.0" refer to the QorIQ chassis version to > which the chip complies. > > Chassis Version Example Chips > --------------- ------------- > 1.0 p4080, p5020, p5040 > 2.0 t4240, b4860, t1040 > Better, I will update. > > BTW, this binding and the associated driver really should be called > "qoriq-clock", not "corenet-clock". This would match the compatible > string, and it doesn't really have much to do with corenet (which is part > of the QorIQ chassis v1 and v2, but not *this* part). Do you know if the > chassis v3 clock interface will be similar enough to share a driver? > Doesn't QorIQ include some low-end socs, like p1022, p1020? This driver has nothing to do with these boards. I have no idea about chassis v3. If it has similar clock tree, this driver can be shared. Even the driver can't be used by v3, we can easily add v3 support since it has different Compatible string. Regards, Yuantian > -Scott >
On Wed, 2014-01-22 at 20:47 -0600, Tang Yuantian-B29983 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: 2014年1月23日 星期四 8:44 > > To: Tang Yuantian-B29983 > > Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc- > > dev@lists.ozlabs.org; devicetree@vger.kernel.org; Kushwaha Prabhakar- > > B32579 > > Subject: Re: [PATCH] clk: corenet: Update the clock bindings > > > > On Tue, 2014-01-21 at 10:02 +0800, Tang Yuantian wrote: > > > From: Tang Yuantian <yuantian.tang@freescale.com> > > > > > > Main changs include: > > > - Clarified the clock nodes' version number > > > - Fixed a issue in example > > > > > > Singed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> > > > --- > > > Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt > > > b/Documentation/devicetree/bindings/clock/corenet-clock.txt > > > index 24711af..d6cadef 100644 > > > --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt > > > +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt > > > @@ -54,6 +54,8 @@ Required properties: > > > It takes parent's clock-frequency as its clock. > > > * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). > > > It takes parent's clock-frequency as its clock. > > > + Note: v1.0 and v2.0 are clock version which should align to > > > + clockgen node's they belong to which is chassis version. > > > > Instead, how about a note like this near the top of the file: > > > > All references to "1.0" and "2.0" refer to the QorIQ chassis version to > > which the chip complies. > > > > Chassis Version Example Chips > > --------------- ------------- > > 1.0 p4080, p5020, p5040 > > 2.0 t4240, b4860, t1040 > > > Better, I will update. > > > > > BTW, this binding and the associated driver really should be called > > "qoriq-clock", not "corenet-clock". This would match the compatible > > string, and it doesn't really have much to do with corenet (which is part > > of the QorIQ chassis v1 and v2, but not *this* part). Do you know if the > > chassis v3 clock interface will be similar enough to share a driver? > > > Doesn't QorIQ include some low-end socs, like p1022, p1020? Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0". They're mpc85xx-family chips. In any case, if "qoriq" makes sense for the compatible, I don't see why it doesn't make sense for the driver. > This driver has nothing to do with these boards. > I have no idea about chassis v3. If it has similar clock tree, this driver can be shared. > Even the driver can't be used by v3, we can easily add v3 support since it has different > Compatible string. The reason I mentioned it is that chassis v3 will involve ARM chips that have their own interconnect rather than corenet. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, 2014-01-23 at 20:33 -0600, Tang Yuantian-B29983 wrote: > > > > Instead, how about a note like this near the top of the file: > > > > > > > > All references to "1.0" and "2.0" refer to the QorIQ chassis version > > > > to which the chip complies. > > > > > > > > Chassis Version Example Chips > > > > --------------- ------------- > > > > 1.0 p4080, p5020, p5040 > > > > 2.0 t4240, b4860, t1040 > > > > > > > Better, I will update. > > > > > > > > > > > BTW, this binding and the associated driver really should be called > > > > "qoriq-clock", not "corenet-clock". This would match the compatible > > > > string, and it doesn't really have much to do with corenet (which is > > > > part of the QorIQ chassis v1 and v2, but not *this* part). Do you > > > > know if the chassis v3 clock interface will be similar enough to > > share a driver? > > > > > > > Doesn't QorIQ include some low-end socs, like p1022, p1020? > > > > Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0". > > They're mpc85xx-family chips. > > > > In any case, if "qoriq" makes sense for the compatible, I don't see why > > it doesn't make sense for the driver. > > > So, "Corenet" is appropriate for driver. > If something should change, that must be compatible string. No. Corenet is a bus interconnect, not a chip family (despite abuse of the name in other contexts in Linux/U-Boot). And the binding with qoriq has already been accepted. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Wood Scott-B07421 > Sent: 2014年1月24日 星期五 10:36 > To: Tang Yuantian-B29983 > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; > devicetree@vger.kernel.org; Kushwaha Prabhakar-B32579 > Subject: Re: [PATCH] clk: corenet: Update the clock bindings > > On Thu, 2014-01-23 at 20:33 -0600, Tang Yuantian-B29983 wrote: > > > > > Instead, how about a note like this near the top of the file: > > > > > > > > > > All references to "1.0" and "2.0" refer to the QorIQ chassis > > > > > version to which the chip complies. > > > > > > > > > > Chassis Version Example Chips > > > > > --------------- ------------- > > > > > 1.0 p4080, p5020, p5040 > > > > > 2.0 t4240, b4860, t1040 > > > > > > > > > Better, I will update. > > > > > > > > > > > > > > BTW, this binding and the associated driver really should be > > > > > called "qoriq-clock", not "corenet-clock". This would match the > > > > > compatible string, and it doesn't really have much to do with > > > > > corenet (which is part of the QorIQ chassis v1 and v2, but not > > > > > *this* part). Do you know if the chassis v3 clock interface > > > > > will be similar enough to > > > share a driver? > > > > > > > > > Doesn't QorIQ include some low-end socs, like p1022, p1020? > > > > > > Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0". > > > They're mpc85xx-family chips. > > > > > > In any case, if "qoriq" makes sense for the compatible, I don't see > > > why it doesn't make sense for the driver. > > > > > So, "Corenet" is appropriate for driver. > > If something should change, that must be compatible string. > > No. Corenet is a bus interconnect, not a chip family (despite abuse of > the name in other contexts in Linux/U-Boot). And the binding with qoriq > has already been accepted. > QorIQ is not the best name either since it include the low-end socs. What the name should be? Regards, Yuantian > -Scott >
On Thu, 2014-01-23 at 20:46 -0600, Tang Yuantian-B29983 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: 2014年1月24日 星期五 10:36 > > To: Tang Yuantian-B29983 > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; > > devicetree@vger.kernel.org; Kushwaha Prabhakar-B32579 > > Subject: Re: [PATCH] clk: corenet: Update the clock bindings > > > > On Thu, 2014-01-23 at 20:33 -0600, Tang Yuantian-B29983 wrote: > > > > > > Instead, how about a note like this near the top of the file: > > > > > > > > > > > > All references to "1.0" and "2.0" refer to the QorIQ chassis > > > > > > version to which the chip complies. > > > > > > > > > > > > Chassis Version Example Chips > > > > > > --------------- ------------- > > > > > > 1.0 p4080, p5020, p5040 > > > > > > 2.0 t4240, b4860, t1040 > > > > > > > > > > > Better, I will update. > > > > > > > > > > > > > > > > > BTW, this binding and the associated driver really should be > > > > > > called "qoriq-clock", not "corenet-clock". This would match the > > > > > > compatible string, and it doesn't really have much to do with > > > > > > corenet (which is part of the QorIQ chassis v1 and v2, but not > > > > > > *this* part). Do you know if the chassis v3 clock interface > > > > > > will be similar enough to > > > > share a driver? > > > > > > > > > > > Doesn't QorIQ include some low-end socs, like p1022, p1020? > > > > > > > > Yes, but those aren't "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0". > > > > They're mpc85xx-family chips. > > > > > > > > In any case, if "qoriq" makes sense for the compatible, I don't see > > > > why it doesn't make sense for the driver. > > > > > > > So, "Corenet" is appropriate for driver. > > > If something should change, that must be compatible string. > > > > No. Corenet is a bus interconnect, not a chip family (despite abuse of > > the name in other contexts in Linux/U-Boot). And the binding with qoriq > > has already been accepted. > > > QorIQ is not the best name either since it include the low-end socs. > What the name should be? Again, those low-end chips do not implement "QorIQ Chassis 1.0" or "QorIQ Chassis 2.0". That they have "QorIQ" in their name is irrelevant. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> > > > > In any case, if "qoriq" makes sense for the compatible, I don't > > > > > see why it doesn't make sense for the driver. > > > > > > > > > So, "Corenet" is appropriate for driver. > > > > If something should change, that must be compatible string. > > > > > > No. Corenet is a bus interconnect, not a chip family (despite abuse > > > of the name in other contexts in Linux/U-Boot). And the binding > > > with qoriq has already been accepted. > > > > > QorIQ is not the best name either since it include the low-end socs. > > What the name should be? > > Again, those low-end chips do not implement "QorIQ Chassis 1.0" or "QorIQ > Chassis 2.0". That they have "QorIQ" in their name is irrelevant. > Got it. Regards, Yuantian > -Scott >
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt index 24711af..d6cadef 100644 --- a/Documentation/devicetree/bindings/clock/corenet-clock.txt +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt @@ -54,6 +54,8 @@ Required properties: It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + Note: v1.0 and v2.0 are clock version which should align to + clockgen node's they belong to which is chassis version. - #clock-cells: From common clock binding. The number of cells in a clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. @@ -85,7 +87,7 @@ Example for clock block and clock provider: #clock-cells = <0>; compatible = "fsl,qoriq-sysclk-1.0"; clock-output-names = "sysclk"; - } + }; pll0: pll0@800 { #clock-cells = <1>;
From: Tang Yuantian <yuantian.tang@freescale.com> Main changs include: - Clarified the clock nodes' version number - Fixed a issue in example Singed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> --- Documentation/devicetree/bindings/clock/corenet-clock.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)