Message ID | 1387399747-4994-3-git-send-email-tommusta@gmail.com |
---|---|
State | New |
Headers | show |
On 12/18/2013 12:48 PM, Tom Musta wrote: > +DEF_HELPER_3(bpermd, i64, env, i64, i64) Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) > +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) > +{ > + int i; > + uint64_t ra = 0; > + > + for (i = 0; i < 8; i++) { > + int index = (rs >> (i*8)) & 0xFF; > + if (index < 64) { > + if (rb & (1ul << (63-index))) { > + ra |= 1 << i; > + } > + } > + } > + return ra; > +} > + You don't need env as an argument; it's unused. Why is all of this specific to ppc64? Can't you run an ISA2.06B machine in 32-bit mode? r~
On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote: > On 12/18/2013 12:48 PM, Tom Musta wrote: > > +DEF_HELPER_3(bpermd, i64, env, i64, i64) > > Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) > > > +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) > > +{ > > + int i; > > + uint64_t ra = 0; > > + > > + for (i = 0; i < 8; i++) { > > + int index = (rs >> (i*8)) & 0xFF; > > + if (index < 64) { > > + if (rb & (1ul << (63-index))) { > > + ra |= 1 << i; > > + } > > + } > > + } > > + return ra; > > +} > > + > > You don't need env as an argument; it's unused. > > Why is all of this specific to ppc64? Can't you run an ISA2.06B machine in > 32-bit mode? bpermd is a 64-bit instruction. 32-bit implementations do not have it. -Scott
On Wed, 2013-12-18 at 14:48 -0600, Tom Musta wrote: > This patch adds the Bit Permute Doubleword (bpermd) instruction, > which was introduced in Power ISA 2.06 as part of the base 64-bit > architecture. Technically it's "Category: Embedded.Phased-in, Server" rather than "Category: Base". e5500 does have it, though, so if IBM's 64-bit booke chips also have it, it might as well be Base. > V2: Addressing stylistic comments from Richard Henderson. > > Signed-off-by: Tom Musta <tommusta@gmail.com> > Reviewed-by: Richard Henderson <address@hidden> > --- > target-ppc/helper.h | 1 + > target-ppc/int_helper.c | 20 ++++++++++++++++++++ > target-ppc/translate.c | 10 ++++++++++ > 3 files changed, 31 insertions(+), 0 deletions(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 6250eba..1ec9c65 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl) > #if defined(TARGET_PPC64) > DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl) > DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl) > +DEF_HELPER_3(bpermd, i64, env, i64, i64) > DEF_HELPER_3(srad, tl, env, tl, tl) > #endif > > diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c > index e50bdd2..abc69a7 100644 > --- a/target-ppc/int_helper.c > +++ b/target-ppc/int_helper.c > @@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t) > } > #endif > > +#if defined(TARGET_PPC64) > + > +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) > +{ > + int i; > + uint64_t ra = 0; > + > + for (i = 0; i < 8; i++) { > + int index = (rs >> (i*8)) & 0xFF; > + if (index < 64) { > + if (rb & (1ul << (63-index))) { 1ull Don't assume that the host is 64-bit -Scott
On 12/27/2013 04:23 PM, Scott Wood wrote: > On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote: >> On 12/18/2013 12:48 PM, Tom Musta wrote: >>> +DEF_HELPER_3(bpermd, i64, env, i64, i64) >> >> Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) >> >>> +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) >>> +{ >>> + int i; >>> + uint64_t ra = 0; >>> + >>> + for (i = 0; i < 8; i++) { >>> + int index = (rs >> (i*8)) & 0xFF; >>> + if (index < 64) { >>> + if (rb & (1ul << (63-index))) { >>> + ra |= 1 << i; >>> + } >>> + } >>> + } >>> + return ra; >>> +} >>> + >> >> You don't need env as an argument; it's unused. >> >> Why is all of this specific to ppc64? Can't you run an ISA2.06B machine in >> 32-bit mode? > > bpermd is a 64-bit instruction. 32-bit implementations do not have it. What has that got to do with running a 64-bit chip in 32-bit mode? r~
> Am 30.12.2013 um 15:48 schrieb Richard Henderson <rth@twiddle.net>: > >> On 12/27/2013 04:23 PM, Scott Wood wrote: >>> On Tue, 2013-12-24 at 07:17 -0800, Richard Henderson wrote: >>>> On 12/18/2013 12:48 PM, Tom Musta wrote: >>>> +DEF_HELPER_3(bpermd, i64, env, i64, i64) >>> >>> Should be DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64) >>> >>>> +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) >>>> +{ >>>> + int i; >>>> + uint64_t ra = 0; >>>> + >>>> + for (i = 0; i < 8; i++) { >>>> + int index = (rs >> (i*8)) & 0xFF; >>>> + if (index < 64) { >>>> + if (rb & (1ul << (63-index))) { >>>> + ra |= 1 << i; >>>> + } >>>> + } >>>> + } >>>> + return ra; >>>> +} >>>> + >>> >>> You don't need env as an argument; it's unused. >>> >>> Why is all of this specific to ppc64? Can't you run an ISA2.06B machine in >>> 32-bit mode? >> >> bpermd is a 64-bit instruction. 32-bit implementations do not have it. > > What has that got to do with running a 64-bit chip in 32-bit mode? Yes you can, but we only expose 64bit capable cpus with TARGET_PPC64 defined. You couldn't select them with the 32bit target. There is even a special linux user target that loads 32bit binaries with the 64bit emulator and 32bit syscall wrapper. Or are you referring to something else than the #ifdef TARGET_PPC64? Alex > > > r~ > >
On 12/30/2013 07:43 AM, Alexander Graf wrote:
> Yes you can, but we only expose 64bit capable cpus with TARGET_PPC64 defined. You couldn't select them with the 32bit target.
Ah, well. That answers my question then, really.
r~
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 6250eba..1ec9c65 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_3(bpermd, i64, env, i64, i64) DEF_HELPER_3(srad, tl, env, tl, tl) #endif diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index e50bdd2..abc69a7 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t) } #endif +#if defined(TARGET_PPC64) + +uint64_t helper_bpermd(CPUPPCState *env, uint64_t rs, uint64_t rb) +{ + int i; + uint64_t ra = 0; + + for (i = 0; i < 8; i++) { + int index = (rs >> (i*8)) & 0xFF; + if (index < 64) { + if (rb & (1ul << (63-index))) { + ra |= 1 << i; + } + } + } + return ra; +} + +#endif + target_ulong helper_cmpb(target_ulong rs, target_ulong rb) { target_ulong mask = 0xff; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1f7e499..0d39de2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1525,6 +1525,15 @@ static void gen_prtyd(DisasContext *ctx) #endif #if defined(TARGET_PPC64) +/* bpermd */ +static void gen_bpermd(DisasContext *ctx) +{ + gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], cpu_env, + cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); +} +#endif + +#if defined(TARGET_PPC64) /* extsw & extsw. */ GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); @@ -9322,6 +9331,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), +GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_ISA206), #endif GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),