| Message ID | 1386355976-11732-2-git-send-email-qiaowei.ren@intel.com |
|---|---|
| State | New |
| Headers | show |
No... we always ask for cpufeature.h patches separately because they sometimes cause conflicts between branches. Borislav Petkov <bp@alien8.de> wrote: >On Sat, Dec 07, 2013 at 02:52:55AM +0800, Qiaowei Ren wrote: >> >> Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com> >> Signed-off-by: Xudong Hao <xudong.hao@intel.com> >> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> >> --- >> arch/x86/include/asm/cpufeature.h | 2 ++ >> 1 files changed, 2 insertions(+), 0 deletions(-) > >This patch should probably be merged with the next one... > >> >> diff --git a/arch/x86/include/asm/cpufeature.h >b/arch/x86/include/asm/cpufeature.h >> index d3f5c63..6c2738d 100644 >> --- a/arch/x86/include/asm/cpufeature.h >> +++ b/arch/x86/include/asm/cpufeature.h >> @@ -216,6 +216,7 @@ >> #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ >> #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor >Context ID */ >> #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional >Memory */ >> +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ >> #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ >> #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions >*/ >> #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access >Prevention */ >> @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32]; >> #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) >> #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) >> #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) >> +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) > >... and we're trying to not have more of those macros so people should >be simply >using boot_cpu_has(X86_FEATURE_YYY).
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index d3f5c63..6c2738d 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -216,6 +216,7 @@ #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ #define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ +#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ #define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ #define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ @@ -330,6 +331,7 @@ extern const char * const x86_power_flags[32]; #define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2) #define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) #define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) +#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)