diff mbox

Add -mtune=ia support

Message ID 20131205182254.GA17941@intel.com
State New
Headers show

Commit Message

H.J. Lu Dec. 5, 2013, 6:22 p.m. UTC 
Hi,

We'd like to add a new -mtune=ia option for x86 to optimize for both
Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
We will improve it further for Haswell and Silvermont.  Later, we will
update it to future Intel processors.  OK for trunk?

Thanks.


H.J.
---
2013-12-05  H.J. Lu  <hongjiu.lu@intel.com>

	* config.gcc: Support --with-cpu=ia.

	* config/i386/i386.c (cpu_names): Add "ia".
	(processor_alias_table): Likewise.
	(ix86_option_override_internal): Disallow -march=ia.
	* config/i386/i386.h (target_cpu_default): Add
	TARGET_CPU_DEFAULT_ia.

	* doc/invoke.texi: Document -mtune=ia.

Comments

Uros Bizjak Dec. 5, 2013, 8:38 p.m. UTC | #1 
On Thu, Dec 5, 2013 at 7:22 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:

> We'd like to add a new -mtune=ia option for x86 to optimize for both
> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
> We will improve it further for Haswell and Silvermont.  Later, we will
> update it to future Intel processors.  OK for trunk?
>
> 2013-12-05  H.J. Lu  <hongjiu.lu@intel.com>
>
>         * config.gcc: Support --with-cpu=ia.
>
>         * config/i386/i386.c (cpu_names): Add "ia".
>         (processor_alias_table): Likewise.
>         (ix86_option_override_internal): Disallow -march=ia.
>         * config/i386/i386.h (target_cpu_default): Add
>         TARGET_CPU_DEFAULT_ia.
>
>         * doc/invoke.texi: Document -mtune=ia.

OK for mainline.

This option should also be mentioned in gcc-4.9 changes.html.

Thanks,
Uros.
Patrick Marlier Dec. 5, 2013, 9:02 p.m. UTC | #2 
Hi,

On 12/05/2013 07:22 PM, H.J. Lu wrote:
> We'd like to add a new -mtune=ia option for x86 to optimize for both
> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
> We will improve it further for Haswell and Silvermont.  Later, we will
> update it to future Intel processors.

At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer 
another name but maybe I am the only one to think that.

--
Patrick Marlier
H.J. Lu Dec. 5, 2013, 9:05 p.m. UTC | #3 
On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier
<patrick.marlier@gmail.com> wrote:
> Hi,
>
>
> On 12/05/2013 07:22 PM, H.J. Lu wrote:
>>
>> We'd like to add a new -mtune=ia option for x86 to optimize for both
>> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
>> We will improve it further for Haswell and Silvermont.  Later, we will
>> update it to future Intel processors.
>
>
> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer
> another name but maybe I am the only one to think that.
>

"ia" stands for Intel Architecture.  It is the natural name for
this option.
Richard Biener Dec. 6, 2013, 9:38 a.m. UTC | #4 
On Thu, Dec 5, 2013 at 10:05 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier
> <patrick.marlier@gmail.com> wrote:
>> Hi,
>>
>>
>> On 12/05/2013 07:22 PM, H.J. Lu wrote:
>>>
>>> We'd like to add a new -mtune=ia option for x86 to optimize for both
>>> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
>>> We will improve it further for Haswell and Silvermont.  Later, we will
>>> update it to future Intel processors.
>>
>>
>> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer
>> another name but maybe I am the only one to think that.
>>
>
> "ia" stands for Intel Architecture.  It is the natural name for
> this option.

I think "ia" and the natural "aa" are too obfuscated.  Why didn't you
chose simply "intel" here?  (will the next patch add -mtune=a as
that's natural for "AMD"?)

Please re-consider.

Richard.

> --
> H.J.
Jakub Jelinek Dec. 6, 2013, 9:41 a.m. UTC | #5 
On Fri, Dec 06, 2013 at 10:38:27AM +0100, Richard Biener wrote:
> On Thu, Dec 5, 2013 at 10:05 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> > On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier
> > <patrick.marlier@gmail.com> wrote:
> >> On 12/05/2013 07:22 PM, H.J. Lu wrote:
> >>>
> >>> We'd like to add a new -mtune=ia option for x86 to optimize for both
> >>> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
> >>> We will improve it further for Haswell and Silvermont.  Later, we will
> >>> update it to future Intel processors.
> >>
> >>
> >> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer
> >> another name but maybe I am the only one to think that.
> >>
> >
> > "ia" stands for Intel Architecture.  It is the natural name for
> > this option.
> 
> I think "ia" and the natural "aa" are too obfuscated.  Why didn't you
> chose simply "intel" here?  (will the next patch add -mtune=a as
> that's natural for "AMD"?)
> 
> Please re-consider.

Yeah, please.

	Jakub
Uros Bizjak Dec. 6, 2013, 10:44 a.m. UTC | #6 
On Fri, Dec 6, 2013 at 10:38 AM, Richard Biener
<richard.guenther@gmail.com> wrote:
> On Thu, Dec 5, 2013 at 10:05 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier
>> <patrick.marlier@gmail.com> wrote:
>>> Hi,
>>>
>>>
>>> On 12/05/2013 07:22 PM, H.J. Lu wrote:
>>>>
>>>> We'd like to add a new -mtune=ia option for x86 to optimize for both
>>>> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
>>>> We will improve it further for Haswell and Silvermont.  Later, we will
>>>> update it to future Intel processors.
>>>
>>>
>>> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer
>>> another name but maybe I am the only one to think that.
>>>
>>
>> "ia" stands for Intel Architecture.  It is the natural name for
>> this option.
>
> I think "ia" and the natural "aa" are too obfuscated.  Why didn't you
> chose simply "intel" here?  (will the next patch add -mtune=a as
> that's natural for "AMD"?)

-mtune=intel indeed sounds better.

Uros.
H.J. Lu Dec. 6, 2013, 11:17 a.m. UTC | #7 
On Fri, Dec 6, 2013 at 2:44 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Fri, Dec 6, 2013 at 10:38 AM, Richard Biener
> <richard.guenther@gmail.com> wrote:
>> On Thu, Dec 5, 2013 at 10:05 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Thu, Dec 5, 2013 at 1:02 PM, Patrick Marlier
>>> <patrick.marlier@gmail.com> wrote:
>>>> Hi,
>>>>
>>>>
>>>> On 12/05/2013 07:22 PM, H.J. Lu wrote:
>>>>>
>>>>> We'd like to add a new -mtune=ia option for x86 to optimize for both
>>>>> Haswell and Silvermont.  Currently, -mtune=ia is aliased to -mtune=slm.
>>>>> We will improve it further for Haswell and Silvermont.  Later, we will
>>>>> update it to future Intel processors.
>>>>
>>>>
>>>> At first, 'ia' means to me Itanium, ie IA-64. I would personally prefer
>>>> another name but maybe I am the only one to think that.
>>>>
>>>
>>> "ia" stands for Intel Architecture.  It is the natural name for
>>> this option.
>>
>> I think "ia" and the natural "aa" are too obfuscated.  Why didn't you
>> chose simply "intel" here?  (will the next patch add -mtune=a as

From

http://en.wikipedia.org/wiki/IA

IA-32, Intel Architecture, 32-bit
IA-64, Intel Architecture, 64-bit

>> that's natural for "AMD"?)
>
> -mtune=intel indeed sounds better.
>

We will discuss it internally.

Thanks.
Gerald Pfeifer Dec. 7, 2013, 10:30 a.m. UTC | #8 
On Fri, 6 Dec 2013, H.J. Lu wrote:
> http://en.wikipedia.org/wiki/IA
> 
> IA-32, Intel Architecture, 32-bit
> IA-64, Intel Architecture, 64-bit

And Intel 64 is an implementation of and extension to the 64-bit 
extension of IA-32 created by AMD, totally unrelated to IA-64.

Marketing. :-)

Gerald
diff mbox

Patch

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1f20f18..dd180a0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1398,7 +1398,7 @@  i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
 			TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
 			need_64bit_isa=yes
 			case X"${with_cpu}" in
-			Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)			
+			Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)			
 				;;
 			X)
 				if test x$with_cpu_64 = x; then
@@ -1407,7 +1407,7 @@  i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
 				;;
 			*)
 				echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-				echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+				echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 				exit 1
 				;;
 			esac
@@ -1519,7 +1519,7 @@  i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
 		tmake_file="$tmake_file i386/t-sol2-64"
 		need_64bit_isa=yes
 		case X"${with_cpu}" in
-		Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
+		Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
 			;;
 		X)
 			if test x$with_cpu_64 = x; then
@@ -1528,7 +1528,7 @@  i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
 			;;
 		*)
 			echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-			echo "generic atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+			echo "generic ia atom slm core2 corei7 corei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 			exit 1
 			;;
 		esac
@@ -1604,7 +1604,7 @@  i[34567]86-*-mingw* | x86_64-*-mingw*)
 			if test x$enable_targets = xall; then
 				tm_defines="${tm_defines} TARGET_BI_ARCH=1"
 				case X"${with_cpu}" in
-				Xgeneric|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
+				Xgeneric|Xia|Xatom|Xslm|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver4|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
 					;;
 				X)
 					if test x$with_cpu_64 = x; then
@@ -1613,7 +1613,7 @@  i[34567]86-*-mingw* | x86_64-*-mingw*)
 					;;
 				*)
 					echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
-					echo "generic atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
+					echo "generic ia atom slm core2 corei7 Xcorei7-avx nocona x86-64 bdver4 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
 					exit 1
 					;;
 				esac
@@ -3664,7 +3664,7 @@  case "${target}" in
 				esac
 				# OK
 				;;
-			"" | x86-64 | generic | native \
+			"" | x86-64 | generic | ia | native \
 			| k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \
 			| opteron-sse3 | athlon-fx | bdver4 | bdver3 | bdver2 \
 			| bdver1 | btver2 |  btver1 | amdfam10 | barcelona \
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0f6612d..382f8fb 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2434,6 +2434,7 @@  static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
   "core-avx2",
   "atom",
   "slm",
+  "ia",
   "geode",
   "k6",
   "k6-2",
@@ -3142,6 +3143,9 @@  ix86_option_override_internal (bool main_args_p,
 	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
 	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_AES
 	| PTA_PCLMUL | PTA_RDRND | PTA_MOVBE | PTA_FXSR},
+      {"ia", PROCESSOR_SLM, CPU_SLM,
+	PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
+	| PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16 | PTA_POPCNT | PTA_FXSR},
       {"geode", PROCESSOR_GEODE, CPU_GEODE,
 	PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
       {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
@@ -3628,6 +3632,9 @@  ix86_option_override_internal (bool main_args_p,
   if (!strcmp (opts->x_ix86_arch_string, "generic"))
     error ("generic CPU can be used only for %stune=%s %s",
 	   prefix, suffix, sw);
+  else if (!strcmp (ix86_arch_string, "ia"))
+    error ("ia CPU can be used only for %stune=%s %s",
+	   prefix, suffix, sw);
   else if (!strncmp (opts->x_ix86_arch_string, "generic", 7) || i == pta_size)
     error ("bad value (%s) for %sarch=%s %s",
 	   opts->x_ix86_arch_string, prefix, suffix, sw);
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 113c75e..db81aea 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -626,6 +626,7 @@  enum target_cpu_default
   TARGET_CPU_DEFAULT_haswell,
   TARGET_CPU_DEFAULT_atom,
   TARGET_CPU_DEFAULT_slm,
+  TARGET_CPU_DEFAULT_ia,
 
   TARGET_CPU_DEFAULT_geode,
   TARGET_CPU_DEFAULT_k6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 704d474..ed5b60f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14743,7 +14743,7 @@  then @option{-mtune=pentium4} generates code that is tuned for Pentium 4
 but still runs on i686 machines.
 
 The choices for @var{cpu-type} are the same as for @option{-march}.
-In addition, @option{-mtune} supports an extra choice for @var{cpu-type}:
+In addition, @option{-mtune} supports 2 extra choices for @var{cpu-type}:
 
 @table @samp
 @item generic
@@ -14764,6 +14764,26 @@  indicates the instruction set the compiler can use, and there is no
 generic instruction set applicable to all processors.  In contrast,
 @option{-mtune} indicates the processor (or, in this case, collection of
 processors) for which the code is optimized.
+
+@item ia
+Produce code optimized for the most current Intel processors, which are
+Haswell and Silvermont for this version of GCC.  If you know the CPU
+on which your code will run, then you should use the corresponding
+@option{-mtune} or @option{-march} option instead of @option{-mtune=ia}.
+But, if you want your application performs better on both Haswell and
+Silvermont, then you should use this option.
+
+As new Intel processors are deployed in the marketplace, the behavior of
+this option will change.  Therefore, if you upgrade to a newer version of
+GCC, code generation controlled by this option will change to reflect
+the most current Intel processors at the time that version of GCC is
+released.
+
+There is no @option{-march=ia} option because @option{-march} indicates
+the instruction set the compiler can use, and there is no common
+instruction set applicable to all processors.  In contrast,
+@option{-mtune} indicates the processor (or, in this case, collection of
+processors) for which the code is optimized.
 @end table
 
 @item -mcpu=@var{cpu-type}