@@ -117,14 +117,6 @@ (define_c_enum "unspecv" [
;; Instruction types and attributes
;; -------------------------------------------------------------------
-;; Main data types used by the insntructions
-
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF"
- (const_string "unknown"))
-
-(define_attr "mode2" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF"
- (const_string "unknown"))
-
; The "type" attribute is is included here from AArch32 backend to be able
; to share pipeline descriptions.
(include "../arm/types.md")
@@ -378,7 +370,6 @@ (define_insn "*tb<optab><mode>1"
return \"<tbz>\\t%<w>0, %1, %l2\";
"
[(set_attr "type" "branch")
- (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
(lt (minus (match_dup 2) (pc)) (const_int 32764)))
@@ -399,7 +390,6 @@ (define_insn "*cb<optab><mode>1"
return \"<tbz>\\t%<w>0, <sizem1>, %l1\";
"
[(set_attr "type" "branch")
- (set_attr "mode" "<MODE>")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768))
(lt (minus (match_dup 1) (pc)) (const_int 32764)))
@@ -630,8 +620,7 @@ (define_insn "*mov<mode>_aarch64"
}
[(set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
neon_from_gp<q>,neon_from_gp<q>, neon_dup")
- (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")
- (set_attr "mode" "<MODE>")]
+ (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")]
)
(define_expand "mov<mode>"
@@ -671,7 +660,6 @@ (define_insn "*movsi_aarch64"
fmov\\t%s0, %s1"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,fmov,fmov,fmov")
- (set_attr "mode" "SI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
)
@@ -697,7 +685,6 @@ (define_insn "*movdi_aarch64"
movi\\t%d0, %1"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
adr,adr,fmov,fmov,fmov,fmov")
- (set_attr "mode" "DI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
)
@@ -710,8 +697,7 @@ (define_insn "insv_imm<mode>"
"UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)
&& UINTVAL (operands[1]) % 16 == 0"
"movk\\t%<w>0, %X2, lsl %1"
- [(set_attr "type" "mov_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "mov_imm")]
)
(define_expand "movti"
@@ -743,7 +729,6 @@ (define_insn "*movti_aarch64"
str\\t%q1, %0"
[(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \
load2,store2,store2,f_loadd,f_stored")
- (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
(set_attr "length" "8,8,8,4,4,4,4,4,4")
(set_attr "simd" "*,*,*,yes,*,*,*,*,*")
(set_attr "fp" "*,*,*,*,*,*,*,yes,yes")]
@@ -794,8 +779,7 @@ (define_insn "*movsf_aarch64"
str\\t%w1, %0
mov\\t%w0, %w1"
[(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\
- f_loads,f_stores,f_loads,f_stores,fmov")
- (set_attr "mode" "SF")]
+ f_loads,f_stores,f_loads,f_stores,fmov")]
)
(define_insn "*movdf_aarch64"
@@ -814,8 +798,7 @@ (define_insn "*movdf_aarch64"
str\\t%x1, %0
mov\\t%x0, %x1"
[(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\
- f_loadd,f_stored,f_loadd,f_stored,mov_reg")
- (set_attr "mode" "DF")]
+ f_loadd,f_stored,f_loadd,f_stored,mov_reg")]
)
(define_expand "movtf"
@@ -854,7 +837,6 @@ (define_insn "*movtf_aarch64"
stp\\t%1, %H1, %0"
[(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg")
- (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
(set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*")
(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")]
@@ -883,8 +865,7 @@ (define_insn "load_pair<mode>"
XEXP (operands[1], 0),
GET_MODE_SIZE (<MODE>mode)))"
"ldp\\t%<w>0, %<w>2, %1"
- [(set_attr "type" "load2")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "load2")]
)
;; Operands 0 and 2 are tied together by the final condition; so we allow
@@ -899,8 +880,7 @@ (define_insn "store_pair<mode>"
XEXP (operands[0], 0),
GET_MODE_SIZE (<MODE>mode)))"
"stp\\t%<w>1, %<w>3, %0"
- [(set_attr "type" "store2")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "store2")]
)
;; Operands 1 and 3 are tied together by the final condition; so we allow
@@ -915,8 +895,7 @@ (define_insn "load_pair<mode>"
XEXP (operands[1], 0),
GET_MODE_SIZE (<MODE>mode)))"
"ldp\\t%<w>0, %<w>2, %1"
- [(set_attr "type" "neon_load1_2reg<q>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "neon_load1_2reg<q>")]
)
;; Operands 0 and 2 are tied together by the final condition; so we allow
@@ -931,8 +910,7 @@ (define_insn "store_pair<mode>"
XEXP (operands[0], 0),
GET_MODE_SIZE (<MODE>mode)))"
"stp\\t%<w>1, %<w>3, %0"
- [(set_attr "type" "neon_store1_2reg<q>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "neon_store1_2reg<q>")]
)
;; Load pair with writeback. This is primarily used in function epilogues
@@ -950,8 +928,7 @@ (define_insn "loadwb_pair<GPI:mode>_<P:m
(match_operand:P 5 "const_int_operand" "n"))))])]
"INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
"ldp\\t%<w>2, %<w>3, [%1], %4"
- [(set_attr "type" "load2")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "load2")]
)
;; Store pair with writeback. This is primarily used in function prologues
@@ -969,8 +946,7 @@ (define_insn "storewb_pair<GPI:mode>_<P:
(match_operand:GPI 3 "register_operand" "r"))])]
"INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
"stp\\t%<w>2, %<w>3, [%0, %4]!"
- [(set_attr "type" "store2")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "store2")]
)
;; -------------------------------------------------------------------
@@ -990,8 +966,7 @@ (define_insn "*extendsidi2_aarch64"
"@
sxtw\t%0, %w1
ldrsw\t%0, %1"
- [(set_attr "type" "extend,load1")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "extend,load1")]
)
(define_insn "*zero_extendsidi2_aarch64"
@@ -1001,8 +976,7 @@ (define_insn "*zero_extendsidi2_aarch64"
"@
uxtw\t%0, %w1
ldr\t%w0, %1"
- [(set_attr "type" "extend,load1")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "extend,load1")]
)
(define_expand "<ANY_EXTEND:optab><SHORT:mode><GPI:mode>2"
@@ -1018,8 +992,7 @@ (define_insn "*extend<SHORT:mode><GPI:mo
"@
sxt<SHORT:size>\t%<GPI:w>0, %w1
ldrs<SHORT:size>\t%<GPI:w>0, %1"
- [(set_attr "type" "extend,load1")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "extend,load1")]
)
(define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64"
@@ -1030,8 +1003,7 @@ (define_insn "*zero_extend<SHORT:mode><G
uxt<SHORT:size>\t%<GPI:w>0, %w1
ldr<SHORT:size>\t%w0, %1
ldr\t%<SHORT:size>0, %1"
- [(set_attr "type" "extend,load1,load1")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "extend,load1,load1")]
)
(define_expand "<optab>qihi2"
@@ -1047,8 +1019,7 @@ (define_insn "*<optab>qihi2_aarch64"
"@
<su>xtb\t%w0, %w1
<ldrxt>b\t%w0, %1"
- [(set_attr "type" "extend,load1")
- (set_attr "mode" "HI")]
+ [(set_attr "type" "extend,load1")]
)
;; -------------------------------------------------------------------
@@ -1091,8 +1062,7 @@ (define_insn "*addsi3_aarch64"
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2"
- [(set_attr "type" "alu_imm,alu_reg,alu_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_imm,alu_reg,alu_imm")]
)
;; zero_extend version of above
@@ -1107,8 +1077,7 @@ (define_insn "*addsi3_aarch64_uxtw"
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2"
- [(set_attr "type" "alu_imm,alu_reg,alu_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_imm,alu_reg,alu_imm")]
)
(define_insn "*adddi3_aarch64"
@@ -1124,7 +1093,6 @@ (define_insn "*adddi3_aarch64"
sub\\t%x0, %x1, #%n2
add\\t%d0, %d1, %d2"
[(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg")
- (set_attr "mode" "DI")
(set_attr "simd" "*,*,*,yes")]
)
@@ -1141,8 +1109,7 @@ (define_insn "*add<mode>3_compare0"
adds\\t%<w>0, %<w>1, %<w>2
adds\\t%<w>0, %<w>1, %<w>2
subs\\t%<w>0, %<w>1, #%n2"
- [(set_attr "type" "alus_reg,alus_imm,alus_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
)
;; zero_extend version of above
@@ -1159,8 +1126,7 @@ (define_insn "*addsi3_compare0_uxtw"
adds\\t%w0, %w1, %w2
adds\\t%w0, %w1, %w2
subs\\t%w0, %w1, #%n2"
- [(set_attr "type" "alus_reg,alus_imm,alus_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
)
(define_insn "*adds_mul_imm_<mode>"
@@ -1176,8 +1142,7 @@ (define_insn "*adds_mul_imm_<mode>"
(match_dup 3)))]
""
"adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alus_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_shift_imm")]
)
(define_insn "*subs_mul_imm_<mode>"
@@ -1193,8 +1158,7 @@ (define_insn "*subs_mul_imm_<mode>"
(mult:GPI (match_dup 2) (match_dup 3))))]
""
"subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
- [(set_attr "type" "alus_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_shift_imm")]
)
(define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>"
@@ -1208,8 +1172,7 @@ (define_insn "*adds_<optab><ALLX:mode>_<
(plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))]
""
"adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alus_ext")]
)
(define_insn "*subs_<optab><ALLX:mode>_<GPI:mode>"
@@ -1223,8 +1186,7 @@ (define_insn "*subs_<optab><ALLX:mode>_<
(minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))]
""
"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alus_ext")]
)
(define_insn "*adds_<optab><mode>_multp2"
@@ -1244,8 +1206,7 @@ (define_insn "*adds_<optab><mode>_multp2
(match_dup 4)))]
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_ext")]
)
(define_insn "*subs_<optab><mode>_multp2"
@@ -1265,8 +1226,7 @@ (define_insn "*subs_<optab><mode>_multp2
(const_int 0))))]
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_ext")]
)
(define_insn "*add<mode>3nr_compare0"
@@ -1280,8 +1240,7 @@ (define_insn "*add<mode>3nr_compare0"
cmn\\t%<w>0, %<w>1
cmn\\t%<w>0, %<w>1
cmp\\t%<w>0, #%n1"
- [(set_attr "type" "alus_reg,alus_imm,alus_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
)
(define_insn "*compare_neg<mode>"
@@ -1291,8 +1250,7 @@ (define_insn "*compare_neg<mode>"
(match_operand:GPI 1 "register_operand" "r")))]
""
"cmn\\t%<w>1, %<w>0"
- [(set_attr "type" "alus_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg")]
)
(define_insn "*add_<shift>_<mode>"
@@ -1302,8 +1260,7 @@ (define_insn "*add_<shift>_<mode>"
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
;; zero_extend version of above
@@ -1315,8 +1272,7 @@ (define_insn "*add_<shift>_si_uxtw"
(match_operand:SI 3 "register_operand" "r"))))]
""
"add\\t%w0, %w3, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "*add_mul_imm_<mode>"
@@ -1326,8 +1282,7 @@ (define_insn "*add_mul_imm_<mode>"
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "*add_<optab><ALLX:mode>_<GPI:mode>"
@@ -1336,8 +1291,7 @@ (define_insn "*add_<optab><ALLX:mode>_<G
(match_operand:GPI 2 "register_operand" "r")))]
""
"add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1348,8 +1302,7 @@ (define_insn "*add_<optab><SHORT:mode>_s
(match_operand:GPI 2 "register_operand" "r"))))]
""
"add\\t%w0, %w2, %w1, <su>xt<SHORT:size>"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*add_<optab><ALLX:mode>_shft_<GPI:mode>"
@@ -1360,8 +1313,7 @@ (define_insn "*add_<optab><ALLX:mode>_sh
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1374,8 +1326,7 @@ (define_insn "*add_<optab><SHORT:mode>_s
(match_operand:SI 3 "register_operand" "r"))))]
""
"add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*add_<optab><ALLX:mode>_mult_<GPI:mode>"
@@ -1386,8 +1337,7 @@ (define_insn "*add_<optab><ALLX:mode>_mu
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1399,8 +1349,7 @@ (define_insn "*add_<optab><SHORT:mode>_m
(match_operand:SI 3 "register_operand" "r"))))]
""
"add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*add_<optab><mode>_multp2"
@@ -1413,8 +1362,7 @@ (define_insn "*add_<optab><mode>_multp2"
(match_operand:GPI 4 "register_operand" "r")))]
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1429,8 +1377,7 @@ (define_insn "*add_<optab>si_multp2_uxtw
(match_operand:SI 4 "register_operand" "r"))))]
"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
"add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*add<mode>3_carryin"
@@ -1442,8 +1389,7 @@ (define_insn "*add<mode>3_carryin"
(match_operand:GPI 2 "register_operand" "r"))))]
""
"adc\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
;; zero_extend version of above
@@ -1457,8 +1403,7 @@ (define_insn "*addsi3_carryin_uxtw"
(match_operand:SI 2 "register_operand" "r")))))]
""
"adc\\t%w0, %w1, %w2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*add<mode>3_carryin_alt1"
@@ -1470,8 +1415,7 @@ (define_insn "*add<mode>3_carryin_alt1"
(geu:GPI (reg:CC CC_REGNUM) (const_int 0))))]
""
"adc\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
;; zero_extend version of above
@@ -1485,8 +1429,7 @@ (define_insn "*addsi3_carryin_alt1_uxtw"
(geu:SI (reg:CC CC_REGNUM) (const_int 0)))))]
""
"adc\\t%w0, %w1, %w2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*add<mode>3_carryin_alt2"
@@ -1498,8 +1441,7 @@ (define_insn "*add<mode>3_carryin_alt2"
(match_operand:GPI 2 "register_operand" "r")))]
""
"adc\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
;; zero_extend version of above
@@ -1513,8 +1455,7 @@ (define_insn "*addsi3_carryin_alt2_uxtw"
(match_operand:SI 2 "register_operand" "r"))))]
""
"adc\\t%w0, %w1, %w2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*add<mode>3_carryin_alt3"
@@ -1526,8 +1467,7 @@ (define_insn "*add<mode>3_carryin_alt3"
(match_operand:GPI 1 "register_operand" "r")))]
""
"adc\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
;; zero_extend version of above
@@ -1541,8 +1481,7 @@ (define_insn "*addsi3_carryin_alt3_uxtw"
(match_operand:SI 1 "register_operand" "r"))))]
""
"adc\\t%w0, %w1, %w2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*add_uxt<mode>_multp2"
@@ -1557,8 +1496,7 @@ (define_insn "*add_uxt<mode>_multp2"
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
INTVAL (operands[3])));
return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1575,8 +1513,7 @@ (define_insn "*add_uxtsi_multp2_uxtw"
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
INTVAL (operands[3])));
return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "subsi3"
@@ -1585,8 +1522,7 @@ (define_insn "subsi3"
(match_operand:SI 2 "register_operand" "r")))]
""
"sub\\t%w0, %w1, %w2"
- [(set_attr "type" "alu_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_reg")]
)
;; zero_extend version of above
@@ -1597,8 +1533,7 @@ (define_insn "*subsi3_uxtw"
(match_operand:SI 2 "register_operand" "r"))))]
""
"sub\\t%w0, %w1, %w2"
- [(set_attr "type" "alu_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_reg")]
)
(define_insn "subdi3"
@@ -1610,7 +1545,6 @@ (define_insn "subdi3"
sub\\t%x0, %x1, %x2
sub\\t%d0, %d1, %d2"
[(set_attr "type" "alu_reg, neon_sub")
- (set_attr "mode" "DI")
(set_attr "simd" "*,yes")]
)
@@ -1624,8 +1558,7 @@ (define_insn "*sub<mode>3_compare0"
(minus:GPI (match_dup 1) (match_dup 2)))]
""
"subs\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "alus_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg")]
)
;; zero_extend version of above
@@ -1638,8 +1571,7 @@ (define_insn "*subsi3_compare0_uxtw"
(zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))]
""
"subs\\t%w0, %w1, %w2"
- [(set_attr "type" "alus_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alus_reg")]
)
(define_insn "*sub_<shift>_<mode>"
@@ -1650,8 +1582,7 @@ (define_insn "*sub_<shift>_<mode>"
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))]
""
"sub\\t%<w>0, %<w>3, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
;; zero_extend version of above
@@ -1664,8 +1595,7 @@ (define_insn "*sub_<shift>_si_uxtw"
(match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
""
"sub\\t%w0, %w3, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "*sub_mul_imm_<mode>"
@@ -1676,8 +1606,7 @@ (define_insn "*sub_mul_imm_<mode>"
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
""
"sub\\t%<w>0, %<w>3, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
;; zero_extend version of above
@@ -1690,8 +1619,7 @@ (define_insn "*sub_mul_imm_si_uxtw"
(match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
""
"sub\\t%w0, %w3, %w1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
@@ -1701,8 +1629,7 @@ (define_insn "*sub_<optab><ALLX:mode>_<G
(match_operand:ALLX 2 "register_operand" "r"))))]
""
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1714,8 +1641,7 @@ (define_insn "*sub_<optab><SHORT:mode>_s
(match_operand:SHORT 2 "register_operand" "r")))))]
""
"sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>"
@@ -1726,8 +1652,7 @@ (define_insn "*sub_<optab><ALLX:mode>_sh
(match_operand 3 "aarch64_imm3" "Ui3"))))]
""
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1740,8 +1665,7 @@ (define_insn "*sub_<optab><SHORT:mode>_s
(match_operand 3 "aarch64_imm3" "Ui3")))))]
""
"sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*sub_<optab><mode>_multp2"
@@ -1754,8 +1678,7 @@ (define_insn "*sub_<optab><mode>_multp2"
(const_int 0))))]
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1770,8 +1693,7 @@ (define_insn "*sub_<optab>si_multp2_uxtw
(const_int 0)))))]
"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
"sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn "*sub<mode>3_carryin"
@@ -1783,8 +1705,7 @@ (define_insn "*sub<mode>3_carryin"
(match_operand:GPI 2 "register_operand" "r")))]
""
"sbc\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
;; zero_extend version of the above
@@ -1798,8 +1719,7 @@ (define_insn "*subsi3_carryin_uxtw"
(match_operand:SI 2 "register_operand" "r"))))]
""
"sbc\\t%w0, %w1, %w2"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*sub_uxt<mode>_multp2"
@@ -1814,8 +1734,7 @@ (define_insn "*sub_uxt<mode>_multp2"
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
INTVAL (operands[3])));
return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_ext")]
)
;; zero_extend version of above
@@ -1832,8 +1751,7 @@ (define_insn "*sub_uxtsi_multp2_uxtw"
operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),
INTVAL (operands[3])));
return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
- [(set_attr "type" "alu_ext")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_ext")]
)
(define_insn_and_split "absdi2"
@@ -1864,8 +1782,7 @@ (define_insn_and_split "absdi2"
GEN_INT (63)))));
DONE;
}
- [(set_attr "type" "alu_reg")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "alu_reg")]
)
(define_insn "neg<mode>2"
@@ -1876,8 +1793,7 @@ (define_insn "neg<mode>2"
neg\\t%<w>0, %<w>1
neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
[(set_attr "type" "alu_reg, neon_neg<q>")
- (set_attr "simd" "*,yes")
- (set_attr "mode" "<MODE>")]
+ (set_attr "simd" "*,yes")]
)
;; zero_extend version of above
@@ -1886,8 +1802,7 @@ (define_insn "*negsi2_uxtw"
(zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))]
""
"neg\\t%w0, %w1"
- [(set_attr "type" "alu_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_reg")]
)
(define_insn "*ngc<mode>"
@@ -1896,8 +1811,7 @@ (define_insn "*ngc<mode>"
(match_operand:GPI 1 "register_operand" "r")))]
""
"ngc\\t%<w>0, %<w>1"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*ngcsi_uxtw"
@@ -1907,8 +1821,7 @@ (define_insn "*ngcsi_uxtw"
(match_operand:SI 1 "register_operand" "r"))))]
""
"ngc\\t%w0, %w1"
- [(set_attr "type" "adc_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "adc_reg")]
)
(define_insn "*neg<mode>2_compare0"
@@ -1919,8 +1832,7 @@ (define_insn "*neg<mode>2_compare0"
(neg:GPI (match_dup 1)))]
""
"negs\\t%<w>0, %<w>1"
- [(set_attr "type" "alus_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg")]
)
;; zero_extend version of above
@@ -1932,8 +1844,7 @@ (define_insn "*negsi2_compare0_uxtw"
(zero_extend:DI (neg:SI (match_dup 1))))]
""
"negs\\t%w0, %w1"
- [(set_attr "type" "alus_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alus_reg")]
)
(define_insn "*neg_<shift><mode>3_compare0"
@@ -1947,8 +1858,7 @@ (define_insn "*neg_<shift><mode>3_compar
(neg:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))))]
""
"negs\\t%<w>0, %<w>1, <shift> %2"
- [(set_attr "type" "alus_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_shift_imm")]
)
(define_insn "*neg_<shift>_<mode>2"
@@ -1958,8 +1868,7 @@ (define_insn "*neg_<shift>_<mode>2"
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))]
""
"neg\\t%<w>0, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
;; zero_extend version of above
@@ -1971,8 +1880,7 @@ (define_insn "*neg_<shift>_si2_uxtw"
(match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
""
"neg\\t%w0, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "*neg_mul_imm_<mode>2"
@@ -1982,8 +1890,7 @@ (define_insn "*neg_mul_imm_<mode>2"
(match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))]
""
"neg\\t%<w>0, %<w>1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_shift_imm")]
)
;; zero_extend version of above
@@ -1995,8 +1902,7 @@ (define_insn "*neg_mul_imm_si2_uxtw"
(match_operand:QI 2 "aarch64_pwr_2_si" "n")))))]
""
"neg\\t%w0, %w1, lsl %p2"
- [(set_attr "type" "alu_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "alu_shift_imm")]
)
(define_insn "mul<mode>3"
@@ -2005,8 +1911,7 @@ (define_insn "mul<mode>3"
(match_operand:GPI 2 "register_operand" "r")))]
""
"mul\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "mul")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "mul")]
)
;; zero_extend version of above
@@ -2017,8 +1922,7 @@ (define_insn "*mulsi3_uxtw"
(match_operand:SI 2 "register_operand" "r"))))]
""
"mul\\t%w0, %w1, %w2"
- [(set_attr "type" "mul")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "mul")]
)
(define_insn "*madd<mode>"
@@ -2028,8 +1932,7 @@ (define_insn "*madd<mode>"
(match_operand:GPI 3 "register_operand" "r")))]
""
"madd\\t%<w>0, %<w>1, %<w>2, %<w>3"
- [(set_attr "type" "mla")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "mla")]
)
;; zero_extend version of above
@@ -2041,8 +1944,7 @@ (define_insn "*maddsi_uxtw"
(match_operand:SI 3 "register_operand" "r"))))]
""
"madd\\t%w0, %w1, %w2, %w3"
- [(set_attr "type" "mla")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "mla")]
)
(define_insn "*msub<mode>"
@@ -2053,8 +1955,7 @@ (define_insn "*msub<mode>"
""
"msub\\t%<w>0, %<w>1, %<w>2, %<w>3"
- [(set_attr "type" "mla")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "mla")]
)
;; zero_extend version of above
@@ -2067,8 +1968,7 @@ (define_insn "*msubsi_uxtw"
""
"msub\\t%w0, %w1, %w2, %w3"
- [(set_attr "type" "mla")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "mla")]
)
(define_insn "*mul<mode>_neg"
@@ -2078,8 +1978,7 @@ (define_insn "*mul<mode>_neg"
""
"mneg\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "mul")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "mul")]
)
;; zero_extend version of above
@@ -2091,8 +1990,7 @@ (define_insn "*mulsi_neg_uxtw"
""
"mneg\\t%w0, %w1, %w2"
- [(set_attr "type" "mul")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "mul")]
)
(define_insn "<su_optab>mulsidi3"
@@ -2101,8 +1999,7 @@ (define_insn "<su_optab>mulsidi3"
(ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))]
""
"<su>mull\\t%0, %w1, %w2"
- [(set_attr "type" "<su>mull")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "<su>mull")]
)
(define_insn "<su_optab>maddsidi4"
@@ -2113,8 +2010,7 @@ (define_insn "<su_optab>maddsidi4"
(match_operand:DI 3 "register_operand" "r")))]
""
"<su>maddl\\t%0, %w1, %w2, %3"
- [(set_attr "type" "<su>mlal")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "<su>mlal")]
)
(define_insn "<su_optab>msubsidi4"
@@ -2126,8 +2022,7 @@ (define_insn "<su_optab>msubsidi4"
(match_operand:SI 2 "register_operand" "r")))))]
""
"<su>msubl\\t%0, %w1, %w2, %3"
- [(set_attr "type" "<su>mlal")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "<su>mlal")]
)
(define_insn "*<su_optab>mulsidi_neg"
@@ -2137,8 +2032,7 @@ (define_insn "*<su_optab>mulsidi_neg"
(ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))]
""
"<su>mnegl\\t%0, %w1, %w2"
- [(set_attr "type" "<su>mull")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "<su>mull")]
)
(define_insn "<su>muldi3_highpart"
@@ -2151,8 +2045,7 @@ (define_insn "<su>muldi3_highpart"
(const_int 64))))]
""
"<su>mulh\\t%0, %1, %2"
- [(set_attr "type" "<su>mull")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "<su>mull")]
)
(define_insn "<su_optab>div<mode>3"
@@ -2161,8 +2054,7 @@ (define_insn "<su_optab>div<mode>3"
(match_operand:GPI 2 "register_operand" "r")))]
""
"<su>div\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "<su>div")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "<su>div")]
)
;; zero_extend version of above
@@ -2173,8 +2065,7 @@ (define_insn "*<su_optab>divsi3_uxtw"
(match_operand:SI 2 "register_operand" "r"))))]
""
"<su>div\\t%w0, %w1, %w2"
- [(set_attr "type" "<su>div")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "<su>div")]
)
;; -------------------------------------------------------------------
@@ -2190,8 +2081,7 @@ (define_insn "*cmp<mode>"
cmp\\t%<w>0, %<w>1
cmp\\t%<w>0, %<w>1
cmn\\t%<w>0, #%n1"
- [(set_attr "type" "alus_reg,alus_imm,alus_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_reg,alus_imm,alus_imm")]
)
(define_insn "*cmp<mode>"
@@ -2202,8 +2092,7 @@ (define_insn "*cmp<mode>"
"@
fcmp\\t%<s>0, #0.0
fcmp\\t%<s>0, %<s>1"
- [(set_attr "type" "fcmp<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fcmp<s>")]
)
(define_insn "*cmpe<mode>"
@@ -2214,8 +2103,7 @@ (define_insn "*cmpe<mode>"
"@
fcmpe\\t%<s>0, #0.0
fcmpe\\t%<s>0, %<s>1"
- [(set_attr "type" "fcmp<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fcmp<s>")]
)
(define_insn "*cmp_swp_<shift>_reg<mode>"
@@ -2226,8 +2114,7 @@ (define_insn "*cmp_swp_<shift>_reg<mode>
(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")))]
""
"cmp\\t%<w>2, %<w>0, <shift> %1"
- [(set_attr "type" "alus_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alus_shift_imm")]
)
(define_insn "*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>"
@@ -2237,8 +2124,7 @@ (define_insn "*cmp_swp_<optab><ALLX:mode
(match_operand:GPI 1 "register_operand" "r")))]
""
"cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alus_ext")]
)
(define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
@@ -2250,8 +2136,7 @@ (define_insn "*cmp_swp_<optab><ALLX:mode
(match_operand:GPI 2 "register_operand" "r")))]
""
"cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
- [(set_attr "type" "alus_ext")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "alus_ext")]
)
;; -------------------------------------------------------------------
@@ -2290,8 +2175,7 @@ (define_insn "*cstore<mode>_insn"
[(match_operand 2 "cc_register" "") (const_int 0)]))]
""
"cset\\t%<w>0, %m1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "csel")]
)
;; zero_extend version of the above
@@ -2302,8 +2186,7 @@ (define_insn "*cstoresi_insn_uxtw"
[(match_operand 2 "cc_register" "") (const_int 0)])))]
""
"cset\\t%w0, %m1"
- [(set_attr "type" "csel")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "csel")]
)
(define_insn "cstore<mode>_neg"
@@ -2312,8 +2195,7 @@ (define_insn "cstore<mode>_neg"
[(match_operand 2 "cc_register" "") (const_int 0)])))]
""
"csetm\\t%<w>0, %m1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "csel")]
)
;; zero_extend version of the above
@@ -2324,8 +2206,7 @@ (define_insn "*cstoresi_neg_uxtw"
[(match_operand 2 "cc_register" "") (const_int 0)]))))]
""
"csetm\\t%w0, %m1"
- [(set_attr "type" "csel")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "csel")]
)
(define_expand "cmov<mode>6"
@@ -2378,8 +2259,7 @@ (define_insn "*cmov<mode>_insn"
csinc\\t%<w>0, %<w>4, <w>zr, %M1
mov\\t%<w>0, -1
mov\\t%<w>0, 1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "csel")]
)
;; zero_extend version of above
@@ -2402,8 +2282,7 @@ (define_insn "*cmovsi_insn_uxtw"
csinc\\t%w0, %w4, wzr, %M1
mov\\t%w0, -1
mov\\t%w0, 1"
- [(set_attr "type" "csel")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "csel")]
)
(define_insn "*cmov<mode>_insn"
@@ -2415,8 +2294,7 @@ (define_insn "*cmov<mode>_insn"
(match_operand:GPF 4 "register_operand" "w")))]
"TARGET_FLOAT"
"fcsel\\t%<s>0, %<s>3, %<s>4, %m1"
- [(set_attr "type" "fcsel")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fcsel")]
)
(define_expand "mov<mode>cc"
@@ -2464,8 +2342,8 @@ (define_insn "*csinc2<mode>_insn"
(match_operand:GPI 1 "register_operand" "r")))]
""
"csinc\\t%<w>0, %<w>1, %<w>1, %M2"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "csel")]
+)
(define_insn "csinc3<mode>_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2477,8 +2355,7 @@ (define_insn "csinc3<mode>_insn"
(match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
""
"csinc\\t%<w>0, %<w>4, %<w>3, %M1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "csel")]
)
(define_insn "*csinv3<mode>_insn"
@@ -2490,8 +2367,8 @@ (define_insn "*csinv3<mode>_insn"
(match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
""
"csinv\\t%<w>0, %<w>4, %<w>3, %M1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "csel")]
+)
(define_insn "*csneg3<mode>_insn"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2502,8 +2379,8 @@ (define_insn "*csneg3<mode>_insn"
(match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))]
""
"csneg\\t%<w>0, %<w>4, %<w>3, %M1"
- [(set_attr "type" "csel")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "csel")]
+)
;; -------------------------------------------------------------------
;; Logical operations
@@ -2515,8 +2392,8 @@ (define_insn "<optab><mode>3"
(match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))]
""
"<logical>\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "logic_reg,logic_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logic_reg,logic_imm")]
+)
;; zero_extend version of above
(define_insn "*<optab>si3_uxtw"
@@ -2526,8 +2403,8 @@ (define_insn "*<optab>si3_uxtw"
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
""
"<logical>\\t%w0, %w1, %w2"
- [(set_attr "type" "logic_reg,logic_imm")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logic_reg,logic_imm")]
+)
(define_insn "*and<mode>3_compare0"
[(set (reg:CC_NZ CC_REGNUM)
@@ -2539,8 +2416,7 @@ (define_insn "*and<mode>3_compare0"
(and:GPI (match_dup 1) (match_dup 2)))]
""
"ands\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "logics_reg,logics_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "logics_reg,logics_imm")]
)
;; zero_extend version of above
@@ -2554,8 +2430,7 @@ (define_insn "*andsi3_compare0_uxtw"
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
""
"ands\\t%w0, %w1, %w2"
- [(set_attr "type" "logics_reg,logics_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "logics_reg,logics_imm")]
)
(define_insn "*and_<SHIFT:optab><mode>3_compare0"
@@ -2570,8 +2445,7 @@ (define_insn "*and_<SHIFT:optab><mode>3_
(and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))]
""
"ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "logics_shift_imm")]
)
;; zero_extend version of above
@@ -2588,8 +2462,7 @@ (define_insn "*and_<SHIFT:optab>si3_comp
(match_dup 3))))]
""
"ands\\t%w0, %w3, %w1, <SHIFT:shift> %2"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "logics_shift_imm")]
)
(define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
@@ -2600,8 +2473,8 @@ (define_insn "*<LOGICAL:optab>_<SHIFT:op
(match_operand:GPI 3 "register_operand" "r")))]
""
"<LOGICAL:logical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
- [(set_attr "type" "logic_shift_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logic_shift_imm")]
+)
;; zero_extend version of above
(define_insn "*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw"
@@ -2613,16 +2486,16 @@ (define_insn "*<LOGICAL:optab>_<SHIFT:op
(match_operand:SI 3 "register_operand" "r"))))]
""
"<LOGICAL:logical>\\t%w0, %w3, %w1, <SHIFT:shift> %2"
- [(set_attr "type" "logic_shift_imm")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logic_shift_imm")]
+)
(define_insn "one_cmpl<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(not:GPI (match_operand:GPI 1 "register_operand" "r")))]
""
"mvn\\t%<w>0, %<w>1"
- [(set_attr "type" "logic_reg")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logic_reg")]
+)
(define_insn "*one_cmpl_<optab><mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2630,8 +2503,8 @@ (define_insn "*one_cmpl_<optab><mode>2"
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))]
""
"mvn\\t%<w>0, %<w>1, <shift> %2"
- [(set_attr "type" "logic_shift_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logic_shift_imm")]
+)
(define_insn "*<LOGICAL:optab>_one_cmpl<mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2640,8 +2513,8 @@ (define_insn "*<LOGICAL:optab>_one_cmpl<
(match_operand:GPI 2 "register_operand" "r")))]
""
"<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1"
- [(set_attr "type" "logic_reg")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logic_reg")]
+)
(define_insn "*and_one_cmpl<mode>3_compare0"
[(set (reg:CC_NZ CC_REGNUM)
@@ -2654,8 +2527,8 @@ (define_insn "*and_one_cmpl<mode>3_compa
(and:GPI (not:GPI (match_dup 1)) (match_dup 2)))]
""
"bics\\t%<w>0, %<w>2, %<w>1"
- [(set_attr "type" "logics_reg")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logics_reg")]
+)
;; zero_extend version of above
(define_insn "*and_one_cmplsi3_compare0_uxtw"
@@ -2669,8 +2542,8 @@ (define_insn "*and_one_cmplsi3_compare0_
(zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
""
"bics\\t%w0, %w2, %w1"
- [(set_attr "type" "logics_reg")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logics_reg")]
+)
(define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2681,8 +2554,8 @@ (define_insn "*<LOGICAL:optab>_one_cmpl_
(match_operand:GPI 3 "register_operand" "r")))]
""
"<LOGICAL:nlogical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logics_shift_imm")]
+)
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
[(set (reg:CC_NZ CC_REGNUM)
@@ -2699,8 +2572,8 @@ (define_insn "*and_one_cmpl_<SHIFT:optab
(match_dup 1) (match_dup 2))) (match_dup 3)))]
""
"bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logics_shift_imm")]
+)
;; zero_extend version of above
(define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
@@ -2718,16 +2591,16 @@ (define_insn "*and_one_cmpl_<SHIFT:optab
(SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))]
""
"bics\\t%w0, %w3, %w1, <SHIFT:shift> %2"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logics_shift_imm")]
+)
(define_insn "clz<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
""
"clz\\t%<w>0, %<w>1"
- [(set_attr "type" "clz")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "clz")]
+)
(define_expand "ffs<mode>2"
[(match_operand:GPI 0 "register_operand")
@@ -2749,16 +2622,16 @@ (define_insn "clrsb<mode>2"
(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))]
""
"cls\\t%<w>0, %<w>1"
- [(set_attr "type" "clz")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "clz")]
+)
(define_insn "rbit<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_RBIT))]
""
"rbit\\t%<w>0, %<w>1"
- [(set_attr "type" "rbit")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "rbit")]
+)
(define_expand "ctz<mode>2"
[(match_operand:GPI 0 "register_operand")
@@ -2779,8 +2652,8 @@ (define_insn "*and<mode>3nr_compare0"
(const_int 0)))]
""
"tst\\t%<w>0, %<w>1"
- [(set_attr "type" "logics_reg")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logics_reg")]
+)
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
[(set (reg:CC_NZ CC_REGNUM)
@@ -2792,8 +2665,8 @@ (define_insn "*and_<SHIFT:optab><mode>3n
(const_int 0)))]
""
"tst\\t%<w>2, %<w>0, <SHIFT:shift> %1"
- [(set_attr "type" "logics_shift_imm")
- (set_attr "mode" "<MODE>")])
+ [(set_attr "type" "logics_shift_imm")]
+)
;; -------------------------------------------------------------------
;; Shifts
@@ -2894,8 +2767,7 @@ (define_insn "*aarch64_ashl_sisd_or_int_
ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>
lsl\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")
- (set_attr "mode" "*,*,<MODE>")]
+ (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")]
)
;; Logical right shift using SISD or Integer instruction
@@ -2910,8 +2782,7 @@ (define_insn "*aarch64_lshr_sisd_or_int_
#
lsr\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")
- (set_attr "mode" "*,*,<MODE>")]
+ (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")]
)
(define_split
@@ -2952,8 +2823,7 @@ (define_insn "*aarch64_ashr_sisd_or_int_
#
asr\t%<w>0, %<w>1, %<w>2"
[(set_attr "simd" "yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")
- (set_attr "mode" "*,*,<MODE>")]
+ (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")]
)
(define_split
@@ -3044,8 +2914,7 @@ (define_insn "*ror<mode>3_insn"
(match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>")))]
""
"ror\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "shift_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "shift_reg")]
)
;; zero_extend version of above
@@ -3056,8 +2925,7 @@ (define_insn "*<optab>si3_insn_uxtw"
(match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))]
""
"<shift>\\t%w0, %w1, %w2"
- [(set_attr "type" "shift_reg")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "shift_reg")]
)
(define_insn "*ashl<mode>3_insn"
@@ -3066,8 +2934,7 @@ (define_insn "*ashl<mode>3_insn"
(match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))]
""
"lsl\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "type" "shift_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "shift_reg")]
)
(define_insn "*<optab><mode>3_insn"
@@ -3079,8 +2946,7 @@ (define_insn "*<optab><mode>3_insn"
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "<bfshift>\t%w0, %w1, %2, %3";
}
- [(set_attr "type" "bfm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "*extr<mode>5_insn"
@@ -3092,8 +2958,7 @@ (define_insn "*extr<mode>5_insn"
"UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
"extr\\t%<w>0, %<w>1, %<w>2, %4"
- [(set_attr "type" "shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "shift_imm")]
)
;; zero_extend version of the above
@@ -3107,8 +2972,7 @@ (define_insn "*extrsi5_insn_uxtw"
"UINTVAL (operands[3]) < 32 &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
"extr\\t%w0, %w1, %w2, %4"
- [(set_attr "type" "shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "shift_imm")]
)
(define_insn "*ror<mode>3_insn"
@@ -3120,8 +2984,7 @@ (define_insn "*ror<mode>3_insn"
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "ror\\t%<w>0, %<w>1, %3";
}
- [(set_attr "type" "shift_imm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "shift_imm")]
)
;; zero_extend version of the above
@@ -3135,8 +2998,7 @@ (define_insn "*rorsi3_insn_uxtw"
operands[3] = GEN_INT (32 - UINTVAL (operands[2]));
return "ror\\t%w0, %w1, %3";
}
- [(set_attr "type" "shift_imm")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "shift_imm")]
)
(define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>"
@@ -3149,8 +3011,7 @@ (define_insn "*<ANY_EXTEND:optab><GPI:mo
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
@@ -3163,8 +3024,7 @@ (define_insn "*zero_extend<GPI:mode>_lsh
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
@@ -3177,8 +3037,7 @@ (define_insn "*extend<GPI:mode>_ashr<SHO
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "bfm")]
)
;; -------------------------------------------------------------------
@@ -3201,8 +3060,7 @@ (define_insn "*<optab><mode>"
(match_operand 3 "const_int_operand" "n")))]
""
"<su>bfx\\t%<w>0, %<w>1, %3, %2"
- [(set_attr "type" "bfm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "bfm")]
)
;; Bitfield Insert (insv)
@@ -3245,8 +3103,7 @@ (define_insn "*insv_reg<mode>"
|| (UINTVAL (operands[2]) + UINTVAL (operands[1])
> GET_MODE_BITSIZE (<MODE>mode)))"
"bfi\\t%<w>0, %<w>3, %2, %1"
- [(set_attr "type" "bfm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "*extr_insv_lower_reg<mode>"
@@ -3260,8 +3117,7 @@ (define_insn "*extr_insv_lower_reg<mode>
|| (UINTVAL (operands[3]) + UINTVAL (operands[1])
> GET_MODE_BITSIZE (<MODE>mode)))"
"bfxil\\t%<w>0, %<w>2, %3, %1"
- [(set_attr "type" "bfm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>"
@@ -3276,8 +3132,7 @@ (define_insn "*<optab><ALLX:mode>_shft_<
: GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
- [(set_attr "type" "bfm")
- (set_attr "mode" "<GPI:MODE>")]
+ [(set_attr "type" "bfm")]
)
;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
@@ -3290,8 +3145,7 @@ (define_insn "*andim_ashift<mode>_bfiz"
"exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
&& (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
- [(set_attr "type" "bfm")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "bfm")]
)
(define_insn "bswap<mode>2"
@@ -3299,8 +3153,7 @@ (define_insn "bswap<mode>2"
(bswap:GPI (match_operand:GPI 1 "register_operand" "r")))]
""
"rev\\t%<w>0, %<w>1"
- [(set_attr "type" "rev")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "rev")]
)
(define_insn "bswaphi2"
@@ -3308,8 +3161,7 @@ (define_insn "bswaphi2"
(bswap:HI (match_operand:HI 1 "register_operand" "r")))]
""
"rev16\\t%w0, %w1"
- [(set_attr "type" "rev")
- (set_attr "mode" "HI")]
+ [(set_attr "type" "rev")]
)
;; zero_extend version of above
@@ -3318,8 +3170,7 @@ (define_insn "*bswapsi2_uxtw"
(zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))]
""
"rev\\t%w0, %w1"
- [(set_attr "type" "rev")
- (set_attr "mode" "SI")]
+ [(set_attr "type" "rev")]
)
;; -------------------------------------------------------------------
@@ -3335,8 +3186,7 @@ (define_insn "<frint_pattern><mode>2"
FRINT))]
"TARGET_FLOAT"
"frint<frint_suffix>\\t%<s>0, %<s>1"
- [(set_attr "type" "f_rint<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "f_rint<s>")]
)
;; frcvt floating-point round to integer and convert standard patterns.
@@ -3347,9 +3197,7 @@ (define_insn "l<fcvt_pattern><su_optab><
FCVT)))]
"TARGET_FLOAT"
"fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1"
- [(set_attr "type" "f_cvtf2i")
- (set_attr "mode" "<GPF:MODE>")
- (set_attr "mode2" "<GPI:MODE>")]
+ [(set_attr "type" "f_cvtf2i")]
)
;; fma - no throw
@@ -3361,8 +3209,7 @@ (define_insn "fma<mode>4"
(match_operand:GPF 3 "register_operand" "w")))]
"TARGET_FLOAT"
"fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmac<s>")]
)
(define_insn "fnma<mode>4"
@@ -3372,8 +3219,7 @@ (define_insn "fnma<mode>4"
(match_operand:GPF 3 "register_operand" "w")))]
"TARGET_FLOAT"
"fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmac<s>")]
)
(define_insn "fms<mode>4"
@@ -3383,8 +3229,7 @@ (define_insn "fms<mode>4"
(neg:GPF (match_operand:GPF 3 "register_operand" "w"))))]
"TARGET_FLOAT"
"fnmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmac<s>")]
)
(define_insn "fnms<mode>4"
@@ -3394,8 +3239,7 @@ (define_insn "fnms<mode>4"
(neg:GPF (match_operand:GPF 3 "register_operand" "w"))))]
"TARGET_FLOAT"
"fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmac<s>")]
)
;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
@@ -3406,8 +3250,7 @@ (define_insn "*fnmadd<mode>4"
(match_operand:GPF 3 "register_operand" "w"))))]
"!HONOR_SIGNED_ZEROS (<MODE>mode) && TARGET_FLOAT"
"fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmac<s>")]
)
;; -------------------------------------------------------------------
@@ -3419,9 +3262,7 @@ (define_insn "extendsfdf2"
(float_extend:DF (match_operand:SF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fcvt\\t%d0, %s1"
- [(set_attr "type" "f_cvt")
- (set_attr "mode" "DF")
- (set_attr "mode2" "SF")]
+ [(set_attr "type" "f_cvt")]
)
(define_insn "truncdfsf2"
@@ -3429,9 +3270,7 @@ (define_insn "truncdfsf2"
(float_truncate:SF (match_operand:DF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fcvt\\t%s0, %d1"
- [(set_attr "type" "f_cvt")
- (set_attr "mode" "SF")
- (set_attr "mode2" "DF")]
+ [(set_attr "type" "f_cvt")]
)
(define_insn "fix_trunc<GPF:mode><GPI:mode>2"
@@ -3439,9 +3278,7 @@ (define_insn "fix_trunc<GPF:mode><GPI:mo
(fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
- [(set_attr "type" "f_cvtf2i")
- (set_attr "mode" "<GPF:MODE>")
- (set_attr "mode2" "<GPI:MODE>")]
+ [(set_attr "type" "f_cvtf2i")]
)
(define_insn "fixuns_trunc<GPF:mode><GPI:mode>2"
@@ -3449,9 +3286,7 @@ (define_insn "fixuns_trunc<GPF:mode><GPI
(unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
- [(set_attr "type" "f_cvtf2i")
- (set_attr "mode" "<GPF:MODE>")
- (set_attr "mode2" "<GPI:MODE>")]
+ [(set_attr "type" "f_cvtf2i")]
)
(define_insn "float<GPI:mode><GPF:mode>2"
@@ -3459,9 +3294,7 @@ (define_insn "float<GPI:mode><GPF:mode>2
(float:GPF (match_operand:GPI 1 "register_operand" "r")))]
"TARGET_FLOAT"
"scvtf\\t%<GPF:s>0, %<GPI:w>1"
- [(set_attr "type" "f_cvti2f")
- (set_attr "mode" "<GPF:MODE>")
- (set_attr "mode2" "<GPI:MODE>")]
+ [(set_attr "type" "f_cvti2f")]
)
(define_insn "floatuns<GPI:mode><GPF:mode>2"
@@ -3469,9 +3302,7 @@ (define_insn "floatuns<GPI:mode><GPF:mod
(unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))]
"TARGET_FLOAT"
"ucvtf\\t%<GPF:s>0, %<GPI:w>1"
- [(set_attr "type" "f_cvt")
- (set_attr "mode" "<GPF:MODE>")
- (set_attr "mode2" "<GPI:MODE>")]
+ [(set_attr "type" "f_cvt")]
)
;; -------------------------------------------------------------------
@@ -3485,8 +3316,7 @@ (define_insn "add<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fadd\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "fadd<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fadd<s>")]
)
(define_insn "sub<mode>3"
@@ -3496,8 +3326,7 @@ (define_insn "sub<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fsub\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "fadd<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fadd<s>")]
)
(define_insn "mul<mode>3"
@@ -3507,8 +3336,7 @@ (define_insn "mul<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fmul\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "fmul<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmul<s>")]
)
(define_insn "*fnmul<mode>3"
@@ -3518,8 +3346,7 @@ (define_insn "*fnmul<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fnmul\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "fmul<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fmul<s>")]
)
(define_insn "div<mode>3"
@@ -3529,8 +3356,7 @@ (define_insn "div<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fdiv\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "fdiv<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fdiv<s>")]
)
(define_insn "neg<mode>2"
@@ -3538,8 +3364,7 @@ (define_insn "neg<mode>2"
(neg:GPF (match_operand:GPF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fneg\\t%<s>0, %<s>1"
- [(set_attr "type" "ffarith<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "ffarith<s>")]
)
(define_insn "sqrt<mode>2"
@@ -3547,8 +3372,7 @@ (define_insn "sqrt<mode>2"
(sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fsqrt\\t%<s>0, %<s>1"
- [(set_attr "type" "fsqrt<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "fsqrt<s>")]
)
(define_insn "abs<mode>2"
@@ -3556,8 +3380,7 @@ (define_insn "abs<mode>2"
(abs:GPF (match_operand:GPF 1 "register_operand" "w")))]
"TARGET_FLOAT"
"fabs\\t%<s>0, %<s>1"
- [(set_attr "type" "ffarith<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "ffarith<s>")]
)
;; Given that smax/smin do not specify the result when either input is NaN,
@@ -3570,8 +3393,7 @@ (define_insn "smax<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fmaxnm\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "f_minmax<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "f_minmax<s>")]
)
(define_insn "smin<mode>3"
@@ -3580,8 +3402,7 @@ (define_insn "smin<mode>3"
(match_operand:GPF 2 "register_operand" "w")))]
"TARGET_FLOAT"
"fminnm\\t%<s>0, %<s>1, %<s>2"
- [(set_attr "type" "f_minmax<s>")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "f_minmax<s>")]
)
;; -------------------------------------------------------------------
@@ -3614,7 +3435,6 @@ (define_insn "aarch64_movdi_<mode>low"
"reload_completed || reload_in_progress"
"fmov\\t%x0, %d1"
[(set_attr "type" "f_mrc")
- (set_attr "mode" "DI")
(set_attr "length" "4")
])
@@ -3626,7 +3446,6 @@ (define_insn "aarch64_movdi_<mode>high"
"reload_completed || reload_in_progress"
"fmov\\t%x0, %1.d[1]"
[(set_attr "type" "f_mrc")
- (set_attr "mode" "DI")
(set_attr "length" "4")
])
@@ -3637,7 +3456,6 @@ (define_insn "aarch64_mov<mode>high_di"
"reload_completed || reload_in_progress"
"fmov\\t%0.d[1], %x1"
[(set_attr "type" "f_mcr")
- (set_attr "mode" "DI")
(set_attr "length" "4")
])
@@ -3647,7 +3465,6 @@ (define_insn "aarch64_mov<mode>low_di"
"reload_completed || reload_in_progress"
"fmov\\t%d0, %x1"
[(set_attr "type" "f_mcr")
- (set_attr "mode" "DI")
(set_attr "length" "4")
])
@@ -3658,7 +3475,6 @@ (define_insn "aarch64_movtilow_tilow"
"reload_completed || reload_in_progress"
"fmov\\t%d0, %d1"
[(set_attr "type" "f_mcr")
- (set_attr "mode" "DI")
(set_attr "length" "4")
])
@@ -3689,8 +3505,7 @@ (define_insn "add_losym_<mode>"
(match_operand 2 "aarch64_valid_symref" "S")))]
""
"add\\t%<w>0, %<w>1, :lo12:%a2"
- [(set_attr "type" "alu_reg")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "alu_reg")]
)
(define_insn "ldr_got_small_<mode>"
@@ -3701,8 +3516,7 @@ (define_insn "ldr_got_small_<mode>"
UNSPEC_GOTSMALLPIC))]
""
"ldr\\t%<w>0, [%1, #:got_lo12:%a2]"
- [(set_attr "type" "load1")
- (set_attr "mode" "<MODE>")]
+ [(set_attr "type" "load1")]
)
(define_insn "ldr_got_small_sidi"
@@ -3714,8 +3528,7 @@ (define_insn "ldr_got_small_sidi"
UNSPEC_GOTSMALLPIC)))]
"TARGET_ILP32"
"ldr\\t%w0, [%1, #:got_lo12:%a2]"
- [(set_attr "type" "load1")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "load1")]
)
(define_insn "ldr_got_tiny"
@@ -3724,8 +3537,7 @@ (define_insn "ldr_got_tiny"
UNSPEC_GOTTINYPIC))]
""
"ldr\\t%0, %L1"
- [(set_attr "type" "load1")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "load1")]
)
(define_insn "aarch64_load_tp_hard"
@@ -3733,8 +3545,7 @@ (define_insn "aarch64_load_tp_hard"
(unspec:DI [(const_int 0)] UNSPEC_TLS))]
""
"mrs\\t%0, tpidr_el0"
- [(set_attr "type" "mrs")
- (set_attr "mode" "DI")]
+ [(set_attr "type" "mrs")]
)
;; The TLS ABI specifically requires that the compiler does not schedule
@@ -3768,7 +3579,6 @@ (define_insn "tlsie_small"
""
"adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]"
[(set_attr "type" "load1")
- (set_attr "mode" "DI")
(set_attr "length" "8")]
)
@@ -3780,7 +3590,6 @@ (define_insn "tlsle_small"
""
"add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2"
[(set_attr "type" "alu_reg")
- (set_attr "mode" "DI")
(set_attr "length" "8")]
)