Message ID | 12410288811793-git-send-email-Haiying.Wang@freescale.com (mailing list archive) |
---|---|
State | Accepted, archived |
Commit | 345f84227b50e90329dd303499024603596566f4 |
Delegated to: | Kumar Gala |
Headers | show |
On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > Change the definition of riscTx and riscRx to unsigned integer > instead of enum, > and change their values to support 4 risc allocation if the qe has 4 > RISC > engines. > > Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> > --- Dave, if you can ack this it is probably easier if this goes via the powerpc tree as it had some dependancies. - k > > drivers/net/ucc_geth.c | 14 +++++++++++--- > drivers/net/ucc_geth.h | 4 ++-- > 2 files changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c > index d3f39e8..3e003fe 100644 > --- a/drivers/net/ucc_geth.c > +++ b/drivers/net/ucc_geth.c > @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct > ucc_geth_private *ugeth, > u8 num_entries, > u32 thread_size, > u32 thread_alignment, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct > ucc_geth_private *ugeth, > static int return_init_enet_entries(struct ucc_geth_private *ugeth, > u32 *p_start, > u8 num_entries, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct > ucc_geth_private *ugeth, > u32 __iomem *p_start, > u8 num_entries, > u32 thread_size, > - enum qe_risc_allocation risc, > + unsigned int risc, > int skip_page_for_first_entry) > { > u32 init_enet_offset; > @@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct > ucc_geth_private *ugeth) > return -ENOMEM; > } > > + /* read the number of risc engines, update the riscTx and riscRx > + * if there are 4 riscs in QE > + */ > + if (qe_get_num_of_risc() == 4) { > + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; > + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; > + } > + > ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); > if (!ugeth->ug_regs) { > if (netif_msg_probe(ugeth)) > diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h > index 2f8ee7c..46bb1d2 100644 > --- a/drivers/net/ucc_geth.h > +++ b/drivers/net/ucc_geth.h > @@ -1120,8 +1120,8 @@ struct ucc_geth_info { > enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; > enum ucc_geth_num_of_threads numThreadsTx; > enum ucc_geth_num_of_threads numThreadsRx; > - enum qe_risc_allocation riscTx; > - enum qe_risc_allocation riscRx; > + unsigned int riscTx; > + unsigned int riscRx; > }; > > /* structure representing UCC GETH */ > -- > 1.6.0.2
From: Kumar Gala <galak@kernel.crashing.org> Date: Wed, 29 Apr 2009 15:23:21 -0500 > > On Apr 29, 2009, at 1:14 PM, Haiying Wang wrote: > >> Change the definition of riscTx and riscRx to unsigned integer instead >> of enum, >> and change their values to support 4 risc allocation if the qe has 4 >> RISC >> engines. >> >> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> >> --- > > Dave, if you can ack this it is probably easier if this goes via the > powerpc tree as it had some dependancies. Fair enough: Acked-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index d3f39e8..3e003fe 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c @@ -270,7 +270,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, u8 num_entries, u32 thread_size, u32 thread_alignment, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -307,7 +307,7 @@ static int fill_init_enet_entries(struct ucc_geth_private *ugeth, static int return_init_enet_entries(struct ucc_geth_private *ugeth, u32 *p_start, u8 num_entries, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -342,7 +342,7 @@ static int dump_init_enet_entries(struct ucc_geth_private *ugeth, u32 __iomem *p_start, u8 num_entries, u32 thread_size, - enum qe_risc_allocation risc, + unsigned int risc, int skip_page_for_first_entry) { u32 init_enet_offset; @@ -2134,6 +2134,14 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth) return -ENOMEM; } + /* read the number of risc engines, update the riscTx and riscRx + * if there are 4 riscs in QE + */ + if (qe_get_num_of_risc() == 4) { + ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS; + ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS; + } + ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs)); if (!ugeth->ug_regs) { if (netif_msg_probe(ugeth)) diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index 2f8ee7c..46bb1d2 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h @@ -1120,8 +1120,8 @@ struct ucc_geth_info { enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc; enum ucc_geth_num_of_threads numThreadsTx; enum ucc_geth_num_of_threads numThreadsRx; - enum qe_risc_allocation riscTx; - enum qe_risc_allocation riscRx; + unsigned int riscTx; + unsigned int riscRx; }; /* structure representing UCC GETH */
Change the definition of riscTx and riscRx to unsigned integer instead of enum, and change their values to support 4 risc allocation if the qe has 4 RISC engines. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> --- drivers/net/ucc_geth.c | 14 +++++++++++--- drivers/net/ucc_geth.h | 4 ++-- 2 files changed, 13 insertions(+), 5 deletions(-)