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[U-Boot,v2] board/bsc9131rdb: Update IFC timings for NAND flash

Message ID 1378814592-29754-1-git-send-email-prabhakar@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Prabhakar Kushwaha Sept. 10, 2013, 12:03 p.m. UTC 
Current IFC timings for NAND flash are not able to support existing
K9F1G08U0B and new K9F1G08U0D flash.

so Update the timings to support both.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: updated subject

 include/configs/BSC9131RDB.h |   16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Comments

York Sun Sept. 27, 2013, 5:54 p.m. UTC | #1 
On 09/10/2013 05:03 AM, Prabhakar Kushwaha wrote:
> Current IFC timings for NAND flash are not able to support existing
> K9F1G08U0B and new K9F1G08U0D flash.
> 
> so Update the timings to support both.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> 
> ---
> Changes for v2: updated subject
> 

Applied to u-boot-mpc85xx/next, pending merging to u-boot-mpc85xx/master
branch.

York
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Patch

diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index 948394e..1d06c50 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -181,18 +181,18 @@  extern unsigned long get_sdram_size(void);
 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
 
 /* NAND Flash Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x08)  \
-					| FTIM0_NAND_TWP(0x06)   \
-					| FTIM0_NAND_TWCHT(0x03) \
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
 					| FTIM0_NAND_TWH(0x04))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x18) \
-					| FTIM1_NAND_TWBE(0x23) \
-					| FTIM1_NAND_TRR(0x08)  \
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
 					| FTIM1_NAND_TRP(0x05))
 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
 					| FTIM2_NAND_TREH(0x04) \
-					| FTIM2_NAND_TWHRE(0x3f))
-#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x22)
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1