diff mbox

[v4,1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define

Message ID 1380014871-22937-1-git-send-email-dongsheng.wang@freescale.com (mailing list archive)
State Accepted, archived
Commit 71a6fa17e1526d3f26f4711cc55d339f96c49a95
Headers show

Commit Message

Dongsheng Wang Sept. 24, 2013, 9:27 a.m. UTC 
From: Wang Dongsheng <dongsheng.wang@freescale.com>

E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Add bit definitions for PWRMGTCR0.

 arch/powerpc/include/asm/reg.h       | 2 ++
 arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
 2 files changed, 11 insertions(+)

Comments

Bharat Bhushan Sept. 24, 2013, 11:21 a.m. UTC | #1 
> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+bharat.bhushan=freescale.com@lists.ozlabs.org] On Behalf Of Dongsheng
> Wang
> Sent: Tuesday, September 24, 2013 2:58 PM
> To: Wood Scott-B07421
> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
> 
> From: Wang Dongsheng <dongsheng.wang@freescale.com>
> 
> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle
> patches.
> 
> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> ---
> *v3:
> Add bit definitions for PWRMGTCR0.
> 
>  arch/powerpc/include/asm/reg.h       | 2 ++
>  arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 64264bf..d4160ca 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1053,6 +1053,8 @@
>  #define PVR_8560	0x80200000
>  #define PVR_VER_E500V1	0x8020
>  #define PVR_VER_E500V2	0x8021
> +#define PVR_VER_E6500	0x8040
> +
>  /*
>   * For the 8xx processors, all of them report the same PVR family for
>   * the PowerPC core. The various versions of these processors must be diff --
> git a/arch/powerpc/include/asm/reg_booke.h
> b/arch/powerpc/include/asm/reg_booke.h
> index ed8f836..4a6457e 100644
> --- a/arch/powerpc/include/asm/reg_booke.h
> +++ b/arch/powerpc/include/asm/reg_booke.h
> @@ -170,6 +170,7 @@
>  #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1
> */
>  #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
>  #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
> +#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */

Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF.
Also I can see SPRN_ICCR also with same SPRN, how that is possible?

-Bharat

>  #define SPRN_SVR	0x3FF	/* System Version Register */
> 
>  /*
> @@ -216,6 +217,14 @@
>  #define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity
> checking */
>  #define	CCR1_TCS	0x00000080 /* Timer Clock Select */
> 
> +/* Bit definitions for PWRMGTCR0. */
> +#define PWRMGTCR0_PW20_WAIT		(1 << 14) /* PW20 state enable bit */
> +#define PWRMGTCR0_PW20_ENT_SHIFT	8
> +#define PWRMGTCR0_PW20_ENT		0x3F00
> +#define PWRMGTCR0_AV_IDLE_PD_EN		(1 << 22) /* Altivec idle enable */
> +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT	16
> +#define PWRMGTCR0_AV_IDLE_CNT		0x3F0000
> +
>  /* Bit definitions for the MCSR. */
>  #define MCSR_MCS	0x80000000 /* Machine Check Summary */
>  #define MCSR_IB		0x40000000 /* Instruction PLB Error */
> --
> 1.8.0
> 
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
Kumar Gala Sept. 24, 2013, 3:48 p.m. UTC | #2 
On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote:

> 
> 
>> -----Original Message-----
>> From: Linuxppc-dev [mailto:linuxppc-dev-
>> bounces+bharat.bhushan=freescale.com@lists.ozlabs.org] On Behalf Of Dongsheng
>> Wang
>> Sent: Tuesday, September 24, 2013 2:58 PM
>> To: Wood Scott-B07421
>> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
>> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
>> 
>> From: Wang Dongsheng <dongsheng.wang@freescale.com>
>> 
>> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle
>> patches.
>> 
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
>> ---
>> *v3:
>> Add bit definitions for PWRMGTCR0.
>> 
>> arch/powerpc/include/asm/reg.h       | 2 ++
>> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
>> 2 files changed, 11 insertions(+)
>> 
>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>> index 64264bf..d4160ca 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -1053,6 +1053,8 @@
>> #define PVR_8560	0x80200000
>> #define PVR_VER_E500V1	0x8020
>> #define PVR_VER_E500V2	0x8021
>> +#define PVR_VER_E6500	0x8040
>> +
>> /*
>>  * For the 8xx processors, all of them report the same PVR family for
>>  * the PowerPC core. The various versions of these processors must be diff --
>> git a/arch/powerpc/include/asm/reg_booke.h
>> b/arch/powerpc/include/asm/reg_booke.h
>> index ed8f836..4a6457e 100644
>> --- a/arch/powerpc/include/asm/reg_booke.h
>> +++ b/arch/powerpc/include/asm/reg_booke.h
>> @@ -170,6 +170,7 @@
>> #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1
>> */
>> #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
>> #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
>> +#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */
> 
> Is this generic for booke or e6500 specific? I can't see this register either in ISA and EREF.
> Also I can see SPRN_ICCR also with same SPRN, how that is possible?

Its possibly because the register maybe in implementation specific region.  I'm guessing ICCR is a 40x specific register.

- k
Wang Dongsheng-B40534 Sept. 25, 2013, 2:34 a.m. UTC | #3 
> >> /*
> >>  * For the 8xx processors, all of them report the same PVR family for
> >>  * the PowerPC core. The various versions of these processors must be
> >> diff -- git a/arch/powerpc/include/asm/reg_booke.h
> >> b/arch/powerpc/include/asm/reg_booke.h
> >> index ed8f836..4a6457e 100644
> >> --- a/arch/powerpc/include/asm/reg_booke.h
> >> +++ b/arch/powerpc/include/asm/reg_booke.h
> >> @@ -170,6 +170,7 @@
> >> #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status
> Register 1
> >> */
> >> #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
> >> #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register
> */
> >> +#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register
> 0 */
> >
> > Is this generic for booke or e6500 specific? I can't see this register
> either in ISA and EREF.

Yes, now only e6500 have this register. There is no problem in this definition,
because no conflict in FSL platform.

> > Also I can see SPRN_ICCR also with same SPRN, how that is possible?
> 
> Its possibly because the register maybe in implementation specific region.
> I'm guessing ICCR is a 40x specific register.

Yes, kumar is right. Its use only in 4xx series of chips.

ICTC(arch/powerpc/include/asm/reg.h) also use 0x3FB, Its use only in 6xx series of chips.

-dongsheng
Bharat Bhushan Sept. 25, 2013, 3:42 a.m. UTC | #4 
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Tuesday, September 24, 2013 9:19 PM
> To: Bhushan Bharat-R65777
> Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
> 
> 
> On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote:
> 
> >
> >
> >> -----Original Message-----
> >> From: Linuxppc-dev [mailto:linuxppc-dev-
> >> bounces+bharat.bhushan=freescale.com@lists.ozlabs.org] On Behalf Of
> >> bounces+Dongsheng
> >> Wang
> >> Sent: Tuesday, September 24, 2013 2:58 PM
> >> To: Wood Scott-B07421
> >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0
> >> define
> >>
> >> From: Wang Dongsheng <dongsheng.wang@freescale.com>
> >>
> >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
> >> idle patches.
> >>
> >> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> >> ---
> >> *v3:
> >> Add bit definitions for PWRMGTCR0.
> >>
> >> arch/powerpc/include/asm/reg.h       | 2 ++
> >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
> >> 2 files changed, 11 insertions(+)
> >>
> >> diff --git a/arch/powerpc/include/asm/reg.h
> >> b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644
> >> --- a/arch/powerpc/include/asm/reg.h
> >> +++ b/arch/powerpc/include/asm/reg.h
> >> @@ -1053,6 +1053,8 @@
> >> #define PVR_8560	0x80200000
> >> #define PVR_VER_E500V1	0x8020
> >> #define PVR_VER_E500V2	0x8021
> >> +#define PVR_VER_E6500	0x8040
> >> +
> >> /*
> >>  * For the 8xx processors, all of them report the same PVR family for
> >>  * the PowerPC core. The various versions of these processors must be
> >> diff -- git a/arch/powerpc/include/asm/reg_booke.h
> >> b/arch/powerpc/include/asm/reg_booke.h
> >> index ed8f836..4a6457e 100644
> >> --- a/arch/powerpc/include/asm/reg_booke.h
> >> +++ b/arch/powerpc/include/asm/reg_booke.h
> >> @@ -170,6 +170,7 @@
> >> #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1
> >> */
> >> #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
> >> #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
> >> +#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */
> >
> > Is this generic for booke or e6500 specific? I can't see this register either
> in ISA and EREF.
> > Also I can see SPRN_ICCR also with same SPRN, how that is possible?
> 
> Its possibly because the register maybe in implementation specific region.  I'm
> guessing ICCR is a 40x specific register.

Kumar, this seems to create confusion? Although I do not like so many header files but still I think we can have reg_4xx.h, reg_fsl_booke.h etc for implementation specific definitions.

-Bharat

> 
> - k
>
Wang Dongsheng-B40534 Sept. 25, 2013, 5:08 a.m. UTC | #5 
> -----Original Message-----
> From: Bhushan Bharat-R65777
> Sent: Wednesday, September 25, 2013 11:43 AM
> To: Kumar Gala
> Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-
> dev@lists.ozlabs.org
> Subject: RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0
> define
> 
> 
> 
> > -----Original Message-----
> > From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > Sent: Tuesday, September 24, 2013 9:19 PM
> > To: Bhushan Bharat-R65777
> > Cc: Wang Dongsheng-B40534; Wood Scott-B07421;
> > linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and
> > SPRN_PWRMGTCR0 define
> >
> >
> > On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote:
> >
> > >
> > >
> > >> -----Original Message-----
> > >> From: Linuxppc-dev [mailto:linuxppc-dev-
> > >> bounces+bharat.bhushan=freescale.com@lists.ozlabs.org] On Behalf Of
> > >> bounces+Dongsheng
> > >> Wang
> > >> Sent: Tuesday, September 24, 2013 2:58 PM
> > >> To: Wood Scott-B07421
> > >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> > >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and
> > >> SPRN_PWRMGTCR0 define
> > >>
> > >> From: Wang Dongsheng <dongsheng.wang@freescale.com>
> > >>
> > >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent
> > >> pw20/altivec idle patches.
> > >>
> > >> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> > >> ---
> > >> *v3:
> > >> Add bit definitions for PWRMGTCR0.
> > >>
> > >> arch/powerpc/include/asm/reg.h       | 2 ++
> > >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
> > >> 2 files changed, 11 insertions(+)
> > >>
> > >> diff --git a/arch/powerpc/include/asm/reg.h
> > >> b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644
> > >> --- a/arch/powerpc/include/asm/reg.h
> > >> +++ b/arch/powerpc/include/asm/reg.h
> > >> @@ -1053,6 +1053,8 @@
> > >> #define PVR_8560	0x80200000
> > >> #define PVR_VER_E500V1	0x8020
> > >> #define PVR_VER_E500V2	0x8021
> > >> +#define PVR_VER_E6500	0x8040
> > >> +
> > >> /*
> > >>  * For the 8xx processors, all of them report the same PVR family
> > >> for
> > >>  * the PowerPC core. The various versions of these processors must
> > >> be diff -- git a/arch/powerpc/include/asm/reg_booke.h
> > >> b/arch/powerpc/include/asm/reg_booke.h
> > >> index ed8f836..4a6457e 100644
> > >> --- a/arch/powerpc/include/asm/reg_booke.h
> > >> +++ b/arch/powerpc/include/asm/reg_booke.h
> > >> @@ -170,6 +170,7 @@
> > >> #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status
> Register 1
> > >> */
> > >> #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
> > >> #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register
> */
> > >> +#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register
> 0 */
> > >
> > > Is this generic for booke or e6500 specific? I can't see this
> > > register either
> > in ISA and EREF.
> > > Also I can see SPRN_ICCR also with same SPRN, how that is possible?
> >
> > Its possibly because the register maybe in implementation specific
> > region.  I'm guessing ICCR is a 40x specific register.
> 
> Kumar, this seems to create confusion? 
I don't think this define will create a confusion, because this is only SPR number
definition and we already have a document(like EREF, ISA, this register define in
E6500-EREF) to describe these registers. There are no conflicts and other platform
and different platforms for the same register have different purposes, it looks normal.
Instead we should put together, so as to remind that the SPR will be reuse from other platforms.

-dongsheng
diff mbox

Patch

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@ 
 #define PVR_8560	0x80200000
 #define PVR_VER_E500V1	0x8020
 #define PVR_VER_E500V2	0x8021
+#define PVR_VER_E6500	0x8040
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@ 
 #define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1 */
 #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
 #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */
 #define SPRN_SVR	0x3FF	/* System Version Register */
 
 /*
@@ -216,6 +217,14 @@ 
 #define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define	CCR1_TCS	0x00000080 /* Timer Clock Select */
 
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT		(1 << 14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT	8
+#define PWRMGTCR0_PW20_ENT		0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN		(1 << 22) /* Altivec idle enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT	16
+#define PWRMGTCR0_AV_IDLE_CNT		0x3F0000
+
 /* Bit definitions for the MCSR. */
 #define MCSR_MCS	0x80000000 /* Machine Check Summary */
 #define MCSR_IB		0x40000000 /* Instruction PLB Error */