| Message ID | 1379195690-6509-7-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
On 14.09.2013 23:54, Richard Henderson wrote: > And since we're no longer talking about opcodes, merge the 0x1ac02000 > data2 primary opcode with the shift subcode to create the full insn. > > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > tcg/aarch64/tcg-target.c | 49 ++++++++++++++++++++++++------------------------ > 1 file changed, 24 insertions(+), 25 deletions(-) > > diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c > index 99d9884..be6d05a 100644 > --- a/tcg/aarch64/tcg-target.c > +++ b/tcg/aarch64/tcg-target.c > @@ -216,14 +216,13 @@ typedef enum { > INSN_ADDS = 0x2b000000, > INSN_SUB = 0x4b000000, > INSN_SUBS = 0x6b000000, > -} AArch64Insn; > > -enum aarch64_srr_opc { > - SRR_SHL = 0x0, > - SRR_SHR = 0x4, > - SRR_SAR = 0x8, > - SRR_ROR = 0xc > -}; > + /* Data-processing (2 source) instructions */ > + INSN_LSLV = 0x1ac02000, > + INSN_LSRV = 0x1ac02400, > + INSN_ASRV = 0x1ac02800, > + INSN_RORV = 0x1ac02c00, > +} AArch64Insn; > > static inline enum aarch64_ldst_op_data > aarch64_ldst_get_data(TCGOpcode tcg_op) > @@ -472,12 +471,12 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext, > } > > static inline void tcg_out_shiftrot_reg(TCGContext *s, > - enum aarch64_srr_opc opc, TCGType ext, > + AArch64Insn insn, TCGType ext, > TCGReg rd, TCGReg rn, TCGReg rm) > { > /* using 2-source data processing instructions 0x1ac02000 */ > - unsigned int base = ext ? 0x9ac02000 : 0x1ac02000; > - tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd); > + unsigned int base = insn | (ext ? 0x80000000 : 0); > + tcg_out32(s, base | rm << 16 | rn << 5 | rd); > } > > static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, > @@ -1214,47 +1213,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > > case INDEX_op_shl_i64: > case INDEX_op_shl_i32: > - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ > + if (c2) { > tcg_out_shl(s, ext, a0, a1, a2); > - } else { /* LSL / LSLV */ > - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); > + } else { > + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); > } > break; Any reason you strip all comments out? They are supposed to hint the reader about how the tcg operation is implemented. > case INDEX_op_shr_i64: > case INDEX_op_shr_i32: > - if (c2) { /* LSR / UBFM Wd, Wn, m, 31 */ > + if (c2) { > tcg_out_shr(s, ext, a0, a1, a2); > - } else { /* LSR / LSRV */ > - tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2); > + } else { > + tcg_out_shiftrot_reg(s, INSN_LSRV, ext, a0, a1, a2); > } > break; > > case INDEX_op_sar_i64: > case INDEX_op_sar_i32: > - if (c2) { /* ASR / SBFM Wd, Wn, m, 31 */ > + if (c2) { > tcg_out_sar(s, ext, a0, a1, a2); > - } else { /* ASR / ASRV */ > - tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2); > + } else { > + tcg_out_shiftrot_reg(s, INSN_ASRV, ext, a0, a1, a2); > } > break; > > case INDEX_op_rotr_i64: > case INDEX_op_rotr_i32: > - if (c2) { /* ROR / EXTR Wd, Wm, Wm, m */ > + if (c2) { > tcg_out_rotr(s, ext, a0, a1, a2); > - } else { /* ROR / RORV */ > - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2); > + } else { > + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, a2); > } > break; > > case INDEX_op_rotl_i64: > - case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */ > - if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ > + case INDEX_op_rotl_i32: > + if (c2) { > tcg_out_rotl(s, ext, a0, a1, a2); > } else { > tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0); > - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP); > + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, TCG_REG_TMP); > } > break; > >
On 09/16/2013 12:56 AM, Claudio Fontana wrote: >> > case INDEX_op_shl_i64: >> > case INDEX_op_shl_i32: >> > - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ >> > + if (c2) { >> > tcg_out_shl(s, ext, a0, a1, a2); >> > - } else { /* LSL / LSLV */ >> > - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); >> > + } else { >> > + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); >> > } >> > break; > Any reason you strip all comments out? > They are supposed to hint the reader about how the tcg operation is implemented. > Well, LSLV is now there in the code in the form of INSN_LSLV. The comment does nothing additional to hint at what's going on; indeed, "LSL / LSLV" is more confusing than not. As for tcg_out_shl, comments about its implementation are with that function. r~
On 16.09.2013 17:06, Richard Henderson wrote: > On 09/16/2013 12:56 AM, Claudio Fontana wrote: >>>> case INDEX_op_shl_i64: >>>> case INDEX_op_shl_i32: >>>> - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ >>>> + if (c2) { >>>> tcg_out_shl(s, ext, a0, a1, a2); >>>> - } else { /* LSL / LSLV */ >>>> - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); >>>> + } else { >>>> + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); >>>> } >>>> break; >> Any reason you strip all comments out? >> They are supposed to hint the reader about how the tcg operation is implemented. >> > > Well, LSLV is now there in the code in the form of INSN_LSLV. The comment does > nothing additional to hint at what's going on; indeed, "LSL / LSLV" is more > confusing than not. > > As for tcg_out_shl, comments about its implementation are with that function. > > Fair enough. C.
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 99d9884..be6d05a 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -216,14 +216,13 @@ typedef enum { INSN_ADDS = 0x2b000000, INSN_SUB = 0x4b000000, INSN_SUBS = 0x6b000000, -} AArch64Insn; -enum aarch64_srr_opc { - SRR_SHL = 0x0, - SRR_SHR = 0x4, - SRR_SAR = 0x8, - SRR_ROR = 0xc -}; + /* Data-processing (2 source) instructions */ + INSN_LSLV = 0x1ac02000, + INSN_LSRV = 0x1ac02400, + INSN_ASRV = 0x1ac02800, + INSN_RORV = 0x1ac02c00, +} AArch64Insn; static inline enum aarch64_ldst_op_data aarch64_ldst_get_data(TCGOpcode tcg_op) @@ -472,12 +471,12 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext, } static inline void tcg_out_shiftrot_reg(TCGContext *s, - enum aarch64_srr_opc opc, TCGType ext, + AArch64Insn insn, TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm) { /* using 2-source data processing instructions 0x1ac02000 */ - unsigned int base = ext ? 0x9ac02000 : 0x1ac02000; - tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd); + unsigned int base = insn | (ext ? 0x80000000 : 0); + tcg_out32(s, base | rm << 16 | rn << 5 | rd); } static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd, @@ -1214,47 +1213,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i64: case INDEX_op_shl_i32: - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ + if (c2) { tcg_out_shl(s, ext, a0, a1, a2); - } else { /* LSL / LSLV */ - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); } break; case INDEX_op_shr_i64: case INDEX_op_shr_i32: - if (c2) { /* LSR / UBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_shr(s, ext, a0, a1, a2); - } else { /* LSR / LSRV */ - tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSRV, ext, a0, a1, a2); } break; case INDEX_op_sar_i64: case INDEX_op_sar_i32: - if (c2) { /* ASR / SBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_sar(s, ext, a0, a1, a2); - } else { /* ASR / ASRV */ - tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_ASRV, ext, a0, a1, a2); } break; case INDEX_op_rotr_i64: case INDEX_op_rotr_i32: - if (c2) { /* ROR / EXTR Wd, Wm, Wm, m */ + if (c2) { tcg_out_rotr(s, ext, a0, a1, a2); - } else { /* ROR / RORV */ - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, a2); } break; case INDEX_op_rotl_i64: - case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */ - if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ + case INDEX_op_rotl_i32: + if (c2) { tcg_out_rotl(s, ext, a0, a1, a2); } else { tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0); - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP); + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, TCG_REG_TMP); } break;
And since we're no longer talking about opcodes, merge the 0x1ac02000 data2 primary opcode with the shift subcode to create the full insn. Signed-off-by: Richard Henderson <rth@twiddle.net> --- tcg/aarch64/tcg-target.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-)