| Message ID | 1378915410-2262-1-git-send-email-murzin.v@gmail.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | a40a2b670706494610d794927b9aebe77e18af8d |
| Headers | show |
Vladimir Murzin <murzin.v@gmail.com> wrote: > Currently DIVWU stands for *signed* divw opcode: > > 7d 2a 4b 96 divwu r9,r10,r9 > 7d 2a 4b d6 divw r9,r10,r9 > > Use the *unsigned* divw opcode for DIVWU. This looks like it's in only used in the BPF JIT code. Matt, any chance you an ACK/NACK this? Mikey > > Signed-off-by: Vladimir Murzin <murzin.v@gmail.com> > --- > arch/powerpc/include/asm/ppc-opcode.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h > index d7fe9f5..c91842c 100644 > --- a/arch/powerpc/include/asm/ppc-opcode.h > +++ b/arch/powerpc/include/asm/ppc-opcode.h > @@ -218,7 +218,7 @@ > #define PPC_INST_MULLW 0x7c0001d6 > #define PPC_INST_MULHWU 0x7c000016 > #define PPC_INST_MULLI 0x1c000000 > -#define PPC_INST_DIVWU 0x7c0003d6 > +#define PPC_INST_DIVWU 0x7c000396 > #define PPC_INST_RLWINM 0x54000000 > #define PPC_INST_RLDICR 0x78000004 > #define PPC_INST_SLW 0x7c000030 > -- > 1.7.10.4 >
On 12 Sep 2013, at 10:02, Michael Neuling <mikey@neuling.org> wrote: > Vladimir Murzin <murzin.v@gmail.com> wrote: > >> Currently DIVWU stands for *signed* divw opcode: >> >> 7d 2a 4b 96 divwu r9,r10,r9 >> 7d 2a 4b d6 divw r9,r10,r9 >> >> Use the *unsigned* divw opcode for DIVWU. > > This looks like it's in only used in the BPF JIT code. > > Matt, any chance you an ACK/NACK this? Sure, that looks sensible, thanks Vladimir. Acked-by: Matt Evans <matt@ozlabs.org> > > Mikey > >> >> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com> >> --- >> arch/powerpc/include/asm/ppc-opcode.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h >> index d7fe9f5..c91842c 100644 >> --- a/arch/powerpc/include/asm/ppc-opcode.h >> +++ b/arch/powerpc/include/asm/ppc-opcode.h >> @@ -218,7 +218,7 @@ >> #define PPC_INST_MULLW 0x7c0001d6 >> #define PPC_INST_MULHWU 0x7c000016 >> #define PPC_INST_MULLI 0x1c000000 >> -#define PPC_INST_DIVWU 0x7c0003d6 >> +#define PPC_INST_DIVWU 0x7c000396 >> #define PPC_INST_RLWINM 0x54000000 >> #define PPC_INST_RLDICR 0x78000004 >> #define PPC_INST_SLW 0x7c000030 >> -- >> 1.7.10.4 >>
On Thu, Sep 12, 2013 at 10:28:03AM +0930, Matt Evans wrote: > On 12 Sep 2013, at 10:02, Michael Neuling <mikey@neuling.org> wrote: > > > Vladimir Murzin <murzin.v@gmail.com> wrote: > > > >> Currently DIVWU stands for *signed* divw opcode: > >> > >> 7d 2a 4b 96 divwu r9,r10,r9 > >> 7d 2a 4b d6 divw r9,r10,r9 > >> > >> Use the *unsigned* divw opcode for DIVWU. > > > > This looks like it's in only used in the BPF JIT code. > > > > Matt, any chance you an ACK/NACK this? > > Sure, that looks sensible, thanks Vladimir. > > Acked-by: Matt Evans <matt@ozlabs.org> > Thanks! Vladimir > > > > Mikey > > > >> > >> Signed-off-by: Vladimir Murzin <murzin.v@gmail.com> > >> --- > >> arch/powerpc/include/asm/ppc-opcode.h | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h > >> index d7fe9f5..c91842c 100644 > >> --- a/arch/powerpc/include/asm/ppc-opcode.h > >> +++ b/arch/powerpc/include/asm/ppc-opcode.h > >> @@ -218,7 +218,7 @@ > >> #define PPC_INST_MULLW 0x7c0001d6 > >> #define PPC_INST_MULHWU 0x7c000016 > >> #define PPC_INST_MULLI 0x1c000000 > >> -#define PPC_INST_DIVWU 0x7c0003d6 > >> +#define PPC_INST_DIVWU 0x7c000396 > >> #define PPC_INST_RLWINM 0x54000000 > >> #define PPC_INST_RLDICR 0x78000004 > >> #define PPC_INST_SLW 0x7c000030 > >> -- > >> 1.7.10.4 > >>
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index d7fe9f5..c91842c 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -218,7 +218,7 @@ #define PPC_INST_MULLW 0x7c0001d6 #define PPC_INST_MULHWU 0x7c000016 #define PPC_INST_MULLI 0x1c000000 -#define PPC_INST_DIVWU 0x7c0003d6 +#define PPC_INST_DIVWU 0x7c000396 #define PPC_INST_RLWINM 0x54000000 #define PPC_INST_RLDICR 0x78000004 #define PPC_INST_SLW 0x7c000030
Currently DIVWU stands for *signed* divw opcode: 7d 2a 4b 96 divwu r9,r10,r9 7d 2a 4b d6 divw r9,r10,r9 Use the *unsigned* divw opcode for DIVWU. Signed-off-by: Vladimir Murzin <murzin.v@gmail.com> --- arch/powerpc/include/asm/ppc-opcode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)