| Message ID | 16b7467c.1f121.141089f3d81.Coremail.coosty@163.com |
|---|---|
| State | New |
| Headers | show |
attachment is patch files.
Hi, El 10/09/13 13:05, cini escribió: > > It has been tested on a Cubieboard 2. To use SMP you must set ARM_ARCH_TIMER and ARM_ARCH_TIMER_USE_PHYCNT when make xconfig. > If you have any questions or comments please feel free to contact me. Have a wonderful day! First of all, thanks for working on this! It is very much appreciated :) Having said that, it would be nice to get properly split git patches, with a description and signoff tag. You can read Documentation/SubmittingPatches on the kernel tree (I think it's a bit outdated, but it covers the basics), or watch this video from Greg which explains it nicely: https://www.youtube.com/watch?v=LLBrBBImJt4 > # On branch master > # Changes to be committed: > # (use "git reset HEAD <file>..." to unstage) > # > # new file: arch/arm/mach-sunxi/headsmp.S > # new file: arch/arm/mach-sunxi/platform.h > # new file: arch/arm/mach-sunxi/platsmp.c I couldn't find these files on either of your emails by the way > # > # Changes not staged for commit: > # (use "git add <file>..." to update what will be committed) > # (use "git checkout -- <file>..." to discard changes in working directory) > # > # modified: arch/arm/boot/dts/sun7i-a20-cubieboard2.dts > # modified: arch/arm/boot/dts/sun7i-a20.dtsi > # modified: arch/arm/include/asm/arch_timer.h > # modified: arch/arm/mach-sunxi/Makefile > # modified: arch/arm/mach-sunxi/sunxi.c > # modified: drivers/clocksource/Kconfig > # modified: drivers/clocksource/arm_arch_timer.c > > > > > > > > > 1 Add Emac,SMP and Arch_timer support for sunxi A20 patch: > > > > > > > > > diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts > old mode 100644 > new mode 100755 > index 31b76f0..2e9c57c > --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts > +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts > @@ -19,6 +19,22 @@ > compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; > > soc@01c00000 { > + emac: ethernet@01c0b000 { > + pinctrl-names = "default"; > + pinctrl-0 = <&emac_pins_a>; > + phy = <&phy1>; > + status = "okay"; > + }; > + > + mdio@01c0b080 { > + status = "okay"; > + > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > + }; > + > + > pinctrl@01c20800 { > led_pins_cubieboard2: led_pins@0 { > allwinner,pins = "PH20", "PH21"; > diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi > old mode 100644 > new mode 100755 > index 999ff45..4c7dd37 > --- a/arch/arm/boot/dts/sun7i-a20.dtsi > +++ b/arch/arm/boot/dts/sun7i-a20.dtsi > @@ -20,16 +20,18 @@ > #address-cells = <1>; > #size-cells = <0>; > > - cpu@0 { > + cpu0: cpu@0 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > reg = <0>; > + clock-frequency = <1000000000>; Is this frequency correct? I thought A20 cores ran on 900-something MHz > }; > > - cpu@1 { > + cpu1: cpu@1 { > compatible = "arm,cortex-a7"; > device_type = "cpu"; > reg = <1>; > + clock-frequency = <1000000000>; > }; > }; > > @@ -161,12 +163,36 @@ > }; > }; > > + > + > soc@01c00000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > ranges; > > + cc: cpuconfig@01c25c00 { > + compatible = "allwinner,sun7i-cc"; > + reg = <0x01c25c00 0x400>; > + }; > + > + emac: ethernet@01c0b000 { > + compatible = "allwinner,sun4i-emac"; > + reg = <0x01c0b000 0x1000>; > + interrupts = <0 55 1>; > + clocks = <&ahb_gates 17>; > + status = "disabled"; > + }; > + > + mdio: mdio@01c0b080 { > + compatible = "allwinner,sun4i-mdio"; > + reg = <0x01c0b080 0x14>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + > pio: pinctrl@01c20800 { > compatible = "allwinner,sun7i-a20-pinctrl"; > reg = <0x01c20800 0x400>; > @@ -198,6 +224,18 @@ > allwinner,drive = <0>; > allwinner,pull = <0>; > }; > + > + emac_pins_a: emac0@0 { > + allwinner,pins = "PA0", "PA1", "PA2", > + "PA3", "PA4", "PA5", "PA6", > + "PA7", "PA8", "PA9", "PA10", > + "PA11", "PA12", "PA13", "PA14", > + "PA15", "PA16"; > + allwinner,function = "emac"; > + allwinner,drive = <0>; > + allwinner,pull = <0>; > + }; > + > }; > > timer@01c20c00 { > @@ -307,5 +345,15 @@ > #interrupt-cells = <3>; > interrupts = <1 9 0xf04>; > }; > + > + timer { > + compatible ="arm,armv7-timer"; > + interrupts = <1 13 0x308>, > + <1 14 0x308>, > + <1 11 0x308>, > + <1 10 0x308>; > + clock-frequency = <24000000>; > + }; > + > }; > }; > diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile > index 93bebfc..d7f1ef4 100644 > --- a/arch/arm/mach-sunxi/Makefile > +++ b/arch/arm/mach-sunxi/Makefile > @@ -1 +1,3 @@ > obj-$(CONFIG_ARCH_SUNXI) += sunxi.o > +obj-$(CONFIG_ARCH_SUNXI) += platsmp.o > +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c > old mode 100644 > new mode 100755 > index e79fb34..b6ccf20 > --- a/arch/arm/mach-sunxi/sunxi.c > +++ b/arch/arm/mach-sunxi/sunxi.c > @@ -137,8 +137,10 @@ static const char * const sunxi_board_dt_compat[] = { > "allwinner,sun7i-a20", > NULL, > }; > +extern struct smp_operations sunxi7i_smp_ops; > > DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") > + .smp = smp_ops(sunxi7i_smp_ops), > .init_machine = sunxi_dt_init, > .init_time = sunxi_timer_init, > .dt_compat = sunxi_board_dt_compat, > > > > > > > > > /***************************************************/ > /***************************************************/ > /***************************************************/ > 2 Add phy cnt arch timer for ARMv7 support: > diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h > old mode 100644 > new mode 100755 > index 5665134..24c904a > --- a/arch/arm/include/asm/arch_timer.h > +++ b/arch/arm/include/asm/arch_timer.h > @@ -87,6 +87,17 @@ static inline u64 arch_counter_get_cntvct(void) > return cval; > } > > +static inline u64 arch_counter_get_cntpct(void) > +{ > + u64 cval; > + > + isb(); > + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); > + return cval; > +} > + > + > + > static inline void arch_counter_set_user_access(void) > { > u32 cntkctl; > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > old mode 100644 > new mode 100755 > index 41c6946..ae67190 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -109,3 +109,12 @@ config VF_PIT_TIMER > bool > help > Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. > +menu "Clock Source" > + > +config ARM_ARCH_TIMER_USE_PHYCNT > + bool "Use Physical Count Timer" > + depends on ARM_ARCH_TIMER > + ---help--- > + If bootloader dont set Virtual Offset register,Physical Count Timer is needed to replace Virtual Count Timer. > + > +endmenu > diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c > old mode 100644 > new mode 100755 > index fbd9ccd..e2fc20a > --- a/drivers/clocksource/arm_arch_timer.c > +++ b/drivers/clocksource/arm_arch_timer.c > @@ -372,7 +372,11 @@ static u64 arch_counter_get_cntvct_mem(void) > * to exist on arm64. arm doesn't use this before DT is probed so even > * if we don't have the cp15 accessors we won't have a problem. > */ > -u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; > +#ifdef CONFIG_ARM_ARCH_TIMER_USE_PHYCNT > + u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntpct; > +#else > + u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; > +#endif This will certainly not play nice with multiplatform kernel. Is this something we can fix on u-boot to use the virtual count timer as the rest of the platforms do? Cheers, Emilio
>Hi, > >El 10/09/13 13:05, cini escribió: >> >> It has been tested on a Cubieboard 2. To use SMP you must set ARM_ARCH_TIMER and ARM_ARCH_TIMER_USE_PHYCNT when make xconfig. >> If you have any questions or comments please feel free to contact me. Have a wonderful day! > >First of all, thanks for working on this! It is very much appreciated :) > >Having said that, it would be nice to get properly split git patches, >with a description and signoff tag. You can read >Documentation/SubmittingPatches on the kernel tree (I think it's a bit >outdated, but it covers the basics), or watch this video from Greg which >explains it nicely: > >https://www.youtube.com/watch?v=LLBrBBImJt4 > Thanks for your response.This is my first patch.I will notice the problem you said. >> # On branch master >> # Changes to be committed: >> # (use "git reset HEAD <file>..." to unstage) >> # >> # new file: arch/arm/mach-sunxi/headsmp.S >> # new file: arch/arm/mach-sunxi/platform.h >> # new file: arch/arm/mach-sunxi/platsmp.c > >I couldn't find these files on either of your emails by the way > Sorry for thar, I check the patch. as you said,the new files can not found,I will update a new patch including the new files later. >Is this frequency correct? I thought A20 cores ran on 900-something MHz A20 manual said the cpu can run 1.2G. > >This will certainly not play nice with multiplatform kernel. Is this >something we can fix on u-boot to use the virtual count timer as the >rest of the platforms do? > >Cheers, > >EmilioYes, you are right,Phy Count Register can not be accessed in Non-secure PL1 mode when register CNTHCTL.PL1PCTEN=0.So we can set CNTHCTL.PL1PCTEN=1 in bootloader then other multiplatform kernel should run ok with phy count in any mode. If kernel want use virtual count timer ,bootloader should set register CNTVOFF=0.On the other way,I think we can get a new nvct= vct-vntvoff as clksource, then kernel can work well even if CNTVOFF does not set to zero by bootload, I will give the patch later.
This is a new patch(add_smp_emac_archtimer_forA20.patch) including miss files.plz replace old add_smp_emac_archtimer_forA20.patch. This is boot log: Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 3.11.0-next-20130903-dirty (root@cini-VirtualBox) (gcc version 4.7.3 (Sourcery CodeBench Lite 2013.05-24) ) #137 SMP Tue Sep 10 23:13:01 CST 2013 [ 0.000000] CPU: ARMv7 Processor [410fc074] revision 4 (ARMv7), cr=10c53c7d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] Machine: Allwinner A1X (Device Tree), model: Cubietech Cubieboard2 [ 0.000000] Memory policy: ECC disabled, Data cache writealloc [ 0.000000] [sunxi7i_smp_init_cpus] ncores=2 [ 0.000000] PERCPU: Embedded 7 pages/cpu @c0ef6000 s6464 r8192 d14016 u32768 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260624 [ 0.000000] Kernel command line: console=ttyS0,115200 [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Memory: 1032396K/1048576K available (3439K kernel code, 179K rwdata, 980K rodata, 1966K init, 482K bss, 16180K reserved, 270336K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] vmalloc : 0xf0000000 - 0xff000000 ( 240 MB) [ 0.000000] lowmem : 0xc0000000 - 0xef800000 ( 760 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc0458f3c (4420 kB) [ 0.000000] .init : 0xc0459000 - 0xc0644940 (1967 kB) [ 0.000000] .data : 0xc0646000 - 0xc0672ec0 ( 180 kB) [ 0.000000] .bss : 0xc0672ec8 - 0xc06eba54 ( 483 kB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. [ 0.000000] NR_IRQS:16 nr_irqs:16 16 [ 0.000000] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms [ 0.000000] Architected cp15 timer(s) running at 24.00MHz (virt). [ 0.000000] Switching to timer-based delay loop [ 0.000000] sched_clock: ARM arch timer >56 bits at 24000kHz, resolution 41ns [ 0.000000] Console: colour dummy device 80x30 [ 15.060670] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=240000) [ 15.060684] pid_max: default: 32768 minimum: 301 [ 15.060824] Mount-cache hash table entries: 512 [ 15.061500] CPU: Testing write buffer coherency: ok [ 15.061788] CPU0: update cpu_power 1024 [ 15.061801] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 15.061835] Setting up static identity map for 0xc0343f70 - 0xc0343fa4 [ 15.062610] [sunxi7i_boot_secondary] enter cpu 1 [ 15.062674] cc_base is f0020c00 [ 15.073695] CPU1: Booted secondary processor [ 15.073729] CPU1: update cpu_power 1024 [ 15.073735] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 15.073843] Brought up 2 CPUs [ 15.073861] SMP: Total of 2 processors activated. [ 15.073866] CPU: All CPU(s) started in SVC mode. [ 15.074533] devtmpfs: initialized [ 15.077992] VFP support v0.3: implementor 41 architecture 2 part 30 variant 7 rev 4 [ 15.078161] pinctrl core: initialized pinctrl subsystem [ 15.078317] regulator-dummy: no parameters [ 15.079295] NET: Registered protocol family 16 [ 15.079546] DMA: preallocated 256 KiB pool for atomic coherent allocations [ 15.083223] bio: create slab <bio-0> at 0 [ 15.084390] Switched to clocksource arch_sys_counter [ 15.089338] NET: Registered protocol family 2 [ 15.089919] TCP established hash table entries: 8192 (order: 4, 65536 bytes) [ 15.090092] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) [ 15.090212] TCP: Hash tables configured (established 8192 bind 8192) [ 15.090290] TCP: reno registered [ 15.090303] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 15.090359] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 15.090942] RPC: Registered named UNIX socket transport module. [ 15.090955] RPC: Registered udp transport module. [ 15.090960] RPC: Registered tcp transport module. [ 15.090966] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 15.220334] bounce pool size: 64 pages [ 15.227490] NFS: Registering the id_resolver key type [ 15.227577] Key type id_resolver registered [ 15.227586] Key type id_legacy registered [ 15.227601] Installing knfsd (copyright (C) 1996 okir@monad.swb.de). [ 15.228087] fuse init (API version 7.22) [ 15.229159] Key type asymmetric registered [ 15.229171] Asymmetric key parser 'x509' registered [ 15.229369] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254) [ 15.229380] io scheduler noop registered [ 15.229386] io scheduler deadline registered [ 15.229523] io scheduler cfq registered (default) [ 15.231164] sunxi-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver [ 15.262592] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 15.283675] 1c28000.serial: ttyS0 at MMIO 0x1c28000 (irq = 33, base_baud = 1500000) is a U6_16550A [ 15.746682] console [ttyS0] enabled [ 15.755447] brd: module loaded [ 15.758582] sun4i-mdio 1c0b080.mdio: no regulator found [ 15.763792] libphy: sun4i_mii_bus: probed [ 15.804858] sun4i-emac 1c0b000.ethernet: using random MAC address c6:9a:96:62:ad:9b [ 15.814192] sun4i-emac 1c0b000.ethernet: eth0: at f006c000, IRQ 87 MAC: c6:9a:96:62:ad:9b [ 15.822582] mousedev: PS/2 mouse device common for all mice [ 15.828377] sdhci: Secure Digital Host Controller Interface driver [ 15.834470] sdhci: Copyright(c) Pierre Ossman [ 15.838751] sdhci-pltfm: SDHCI platform and OF driver helper [ 15.844936] ipip: IPv4 over IPv4 tunneling driver [ 15.850116] TCP: cubic registered [ 15.853490] Key type dns_resolver registered [ 15.860975] Freeing unused kernel memory: 1964K (c0459000 - c0644000) Fiddlesticks login: Fiddlesticks login: root
Hi Cini, On Wed, Sep 11, 2013 at 12:05:55AM +0800, cini wrote: > It has been tested on a Cubieboard 2. To use SMP you must set > ARM_ARCH_TIMER and ARM_ARCH_TIMER_USE_PHYCNT when make xconfig. If > you have any questions or comments please feel free to contact me. > Have a wonderful day! Thanks for working on this! You still have to work a bit on the submission part however. First, make sure you read and follow http://www.tuxradar.com/content/newbies-guide-hacking-linux-kernel along with Documentation/SubmittingPatches Basically, you should use git format-patch and git send-email to easily contribute your patches to the right format. Among other things, your current patches lack some files (platsmp.c, headsmp.S, etc.), also lack the Signed-off-by tag (using your real name). You should also try to split the changes you're making into logical changes. In that case, that means that you would probably have different patches to : - Add the SMP code to mach-sunxi - Add the SMP-related nodes to the DTSI - Make the modifications to the arch timers - And add the EMAC support Finally, you should probably look at http://linux-sunxi.org/Mainlining_Effort to get in sync with other people doing sunxi-related stuff to avoid effort duplication. Thanks, Maxime
I have send the patch including all files is at http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20130911/eacb841e/attachment-0001.obj in pre mail. I will reupdate the path as you said later. Thanks for your advice.
Hi Cini, very nice work. You could join other people that hack on sunxi kernels using the information here: http://linux-sunxi.org/sunxi:Community_portal Please subscribe to our mailing list to stay tuned. Also, our IRC channel is very active and friendly. Best, Arokux
I have released the new patchs that is clean。 0001-Add-smp-support-for-Allwinner-A20-sunxi-7i.patch 0002-Add-cpuconfig-nodes-in-dts-for-smp-configure.patch 0003-Add-physical-count-arch-timer-support-for-clocksourc.patch 0004-Add-arch-count-timer-node-in-dts-for-Allwinner-A20-s.patch 0005-Add-emac-node-for-Allwinner-A20-sun7i.patch 0006-Add-emac-node-in-dts-for-CubieBoard2.patch
Hi Fan, On Thu, Sep 12, 2013 at 01:45:07AM +0800, cini wrote: > I have released the new patchs that is clean。 > 0001-Add-smp-support-for-Allwinner-A20-sunxi-7i.patch > 0002-Add-cpuconfig-nodes-in-dts-for-smp-configure.patch > 0003-Add-physical-count-arch-timer-support-for-clocksourc.patch > 0004-Add-arch-count-timer-node-in-dts-for-Allwinner-A20-s.patch > 0005-Add-emac-node-for-Allwinner-A20-sun7i.patch > 0006-Add-emac-node-in-dts-for-CubieBoard2.patch Great, you're almost there. Usually, we split up the series by what they are actually doing. In your case, that would mean that you would send two set of patches, one for the SMP support on the A20, and one for your arch timer patches. I already sent a serie about the EMAC, so you can probably drop that one. And to send these two series, you should send your patches in the mail directly. git send-email makes that really easy, so I'd advise you to actually use it. Along with these patches, we most of the time also send a cover letter to introduce what we're doing in these patches, the difficulties/drawbacks we faced, etc. In your case for example, this is pretty much where you should put that you don't use the scu, and why you don't use it. Finally, you should send it the relevant maintainers of the files touched by your patches. You can get it quite easily by using the get_maintainers.pl script in the scripts/ directory. Don't forget to run the scrits/checkpatch.pl script on your patches, and you'll be all set! Thanks for your efforts, Maxime
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts old mode 100644 new mode 100755 index 31b76f0..2e9c57c --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -19,6 +19,22 @@ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + pinctrl@01c20800 { led_pins_cubieboard2: led_pins@0 { allwinner,pins = "PH20", "PH21"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi old mode 100644 new mode 100755 index 999ff45..4c7dd37 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -20,16 +20,18 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clock-frequency = <1000000000>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clock-frequency = <1000000000>; }; }; @@ -161,12 +163,36 @@ }; }; + + soc@01c00000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + cc: cpuconfig@01c25c00 { + compatible = "allwinner,sun7i-cc"; + reg = <0x01c25c00 0x400>; + }; + + emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-emac"; + reg = <0x01c0b000 0x1000>; + interrupts = <0 55 1>; + clocks = <&ahb_gates 17>; + status = "disabled"; + }; + + mdio: mdio@01c0b080 { + compatible = "allwinner,sun4i-mdio"; + reg = <0x01c0b080 0x14>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + pio: pinctrl@01c20800 { compatible = "allwinner,sun7i-a20-pinctrl"; reg = <0x01c20800 0x400>; @@ -198,6 +224,18 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + emac_pins_a: emac0@0 { + allwinner,pins = "PA0", "PA1", "PA2", + "PA3", "PA4", "PA5", "PA6", + "PA7", "PA8", "PA9", "PA10", + "PA11", "PA12", "PA13", "PA14", + "PA15", "PA16"; + allwinner,function = "emac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; timer@01c20c00 { @@ -307,5 +345,15 @@ #interrupt-cells = <3>; interrupts = <1 9 0xf04>; }; + + timer { + compatible ="arm,armv7-timer"; + interrupts = <1 13 0x308>, + <1 14 0x308>, + <1 11 0x308>, + <1 10 0x308>; + clock-frequency = <24000000>; + }; + }; }; diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 93bebfc..d7f1ef4 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi.o +obj-$(CONFIG_ARCH_SUNXI) += platsmp.o +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c old mode 100644 new mode 100755 index e79fb34..b6ccf20 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -137,8 +137,10 @@ static const char * const sunxi_board_dt_compat[] = { "allwinner,sun7i-a20", NULL, }; +extern struct smp_operations sunxi7i_smp_ops; DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)") + .smp = smp_ops(sunxi7i_smp_ops), .init_machine = sunxi_dt_init, .init_time = sunxi_timer_init, .dt_compat = sunxi_board_dt_compat, /***************************************************/ /***************************************************/ /***************************************************/ 2 Add phy cnt arch timer for ARMv7 support: diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h old mode 100644 new mode 100755 index 5665134..24c904a --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -87,6 +87,17 @@ static inline u64 arch_counter_get_cntvct(void) return cval; } +static inline u64 arch_counter_get_cntpct(void) +{ + u64 cval; + + isb(); + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval)); + return cval; +} + + + static inline void arch_counter_set_user_access(void) { u32 cntkctl; diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig old mode 100644 new mode 100755 index 41c6946..ae67190 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -109,3 +109,12 @@ config VF_PIT_TIMER bool help Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. +menu "Clock Source" + +config ARM_ARCH_TIMER_USE_PHYCNT + bool "Use Physical Count Timer" + depends on ARM_ARCH_TIMER + ---help--- + If bootloader dont set Virtual Offset register,Physical Count Timer is needed to replace Virtual Count Timer. + +endmenu diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c old mode 100644 new mode 100755 index fbd9ccd..e2fc20a --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -372,7 +372,11 @@ static u64 arch_counter_get_cntvct_mem(void) * to exist on arm64. arm doesn't use this before DT is probed so even * if we don't have the cp15 accessors we won't have a problem. */ -u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; +#ifdef CONFIG_ARM_ARCH_TIMER_USE_PHYCNT + u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntpct; +#else + u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct; +#endif static cycle_t arch_counter_read(struct clocksource *cs) { @@ -409,8 +413,12 @@ static void __init arch_counter_register(unsigned type) u64 start_count; /* Register the CP15 based counter if we have one */ - if (type & ARCH_CP15_TIMER) + if (type & ARCH_CP15_TIMER) +#ifdef CONFIG_ARM_ARCH_TIMER_USE_PHYCNT + arch_timer_read_counter = arch_counter_get_cntpct; +#else arch_timer_read_counter = arch_counter_get_cntvct; +#endif else arch_timer_read_counter = arch_counter_get_cntvct_mem;