| Message ID | 1378452491-20467-2-git-send-email-famz@redhat.com |
|---|---|
| State | New |
| Headers | show |
Fam Zheng writes: [...] > Because $(obj) here is './block', instead of '../block'. This doesn't > hurt compiling because we basically build all .o from top Makefile, > before entering Makefile.target, but it will affact arriving per-object > libs support. I'm curious. What's the reason to not use recursive make in QEMU? Thanks, Lluis
On Fri, 09/06 20:19, Lluís Vilanova wrote: > Fam Zheng writes: > [...] > > Because $(obj) here is './block', instead of '../block'. This doesn't > > hurt compiling because we basically build all .o from top Makefile, > > before entering Makefile.target, but it will affact arriving per-object > > libs support. > > I'm curious. What's the reason to not use recursive make in QEMU? > I don't know the answer, Paolo? Fam
Il 09/09/2013 03:34, Fam Zheng ha scritto: > On Fri, 09/06 20:19, Lluís Vilanova wrote: >> Fam Zheng writes: >> [...] >>> Because $(obj) here is './block', instead of '../block'. This doesn't >>> hurt compiling because we basically build all .o from top Makefile, >>> before entering Makefile.target, but it will affact arriving per-object >>> libs support. >> >> I'm curious. What's the reason to not use recursive make in QEMU? >> > I don't know the answer, Paolo? It predates my involvement by a long time, so I don't know. But my guess is that whenever directories are not present in the build tree (e.g. i386-softmmu/hw) we have to create the Makefile in the configure script. Thus a heavily declarative Makefile style works better. Paolo
On 6 September 2013 18:19, Lluís Vilanova <vilanova@ac.upc.edu> wrote: > Fam Zheng writes: > [...] >> Because $(obj) here is './block', instead of '../block'. This doesn't >> hurt compiling because we basically build all .o from top Makefile, >> before entering Makefile.target, but it will affact arriving per-object >> libs support. > > I'm curious. What's the reason to not use recursive make in QEMU? The classic paper is "Recursive make considered harmful": http://aegis.sourceforge.net/auug97.pdf -- PMM
diff --git a/Makefile.target b/Makefile.target index 9a49852..0ab60bd 100644 --- a/Makefile.target +++ b/Makefile.target @@ -144,12 +144,13 @@ endif # CONFIG_SOFTMMU %/translate.o: QEMU_CFLAGS += $(TRANSLATE_OPT_CFLAGS) nested-vars += obj-y +obj-base := .. # This resolves all nested paths, so it must come last include $(SRC_PATH)/Makefile.objs all-obj-y = $(obj-y) -all-obj-y += $(addprefix ../, $(common-obj-y)) +all-obj-y += $(addprefix $(obj)/, $(common-obj-y)) ifndef CONFIG_HAIKU LIBS+=-lm diff --git a/rules.mak b/rules.mak index 4499745..eef1b71 100644 --- a/rules.mak +++ b/rules.mak @@ -103,7 +103,7 @@ clean: clean-timestamp # magic to descend into other directories -obj := . +obj = $(obj-base) old-nested-dirs := define push-var @@ -119,9 +119,10 @@ endef define unnest-dir $(foreach var,$(nested-vars),$(call push-var,$(var),$1/)) -$(eval obj := $(obj)/$1) +$(eval old-obj := $(obj)) +$(eval obj := $(if $(obj),$(obj)/$1,$1)) $(eval include $(SRC_PATH)/$1/Makefile.objs) -$(eval obj := $(patsubst %/$1,%,$(obj))) +$(eval obj := $(old-obj)) $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/)) endef
Makefile.target includes rule.mak and unnested common-obj-y, then prefix them with '../', this will ignore object specific QEMU_CFLAGS in subdir Makefile.objs: $(obj)/curl.o: QEMU_CFLAGS += $(CURL_CFLAGS) Because $(obj) here is './block', instead of '../block'. This doesn't hurt compiling because we basically build all .o from top Makefile, before entering Makefile.target, but it will affact arriving per-object libs support. The starting point of $(obj) is fixed in $(obj-base) before including ./Makefile.objs, to get consistency with nested Makefile rules in target rule and variable definition. Signed-off-by: Fam Zheng <famz@redhat.com> --- Makefile.target | 3 ++- rules.mak | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-)