Message ID | 1378475306-26392-1-git-send-email-james.greenhalgh@arm.com |
---|---|
State | New |
Headers | show |
On 06/09/13 14:48, James Greenhalgh wrote: > > Hi, > > This patch adds an "mrs" type to be used to categorize instructions > which read or write from a special/system/co-processor register. > > Then we add this type to all the pipeline descriptions. This probably > ends up as a miscategorization in most cases as we put "mrs" in the > same category as "multiple" in the pipelines. This will give the most > consistant behaviour with what came before. > > Regression tested on aarch64-none-elf and arm-none-eabi with no > regressions. > > OK? > > Thanks, > James > > --- > gcc/ > > 2013-09-06 James Greenhalgh <james.greenhalgh@arm.com> > > * config/arm/types.md (type): Add "mrs" type. > * config/aarch64/aarch64.md > (aarch64_load_tp_hard): Make type "mrs". > * config/arm/arm.md > (load_tp_hard): Make type "mrs". > * config/arm/cortex-a15.md: Update with new attributes. > * config/arm/cortex-a5.md: Update with new attributes. > * config/arm/cortex-a53.md: Update with new attributes. > * config/arm/cortex-a7.md: Update with new attributes. > * config/arm/cortex-a8.md: Update with new attributes. > * config/arm/cortex-a9.md: Update with new attributes. > * config/arm/cortex-m4.md: Update with new attributes. > * config/arm/cortex-r4.md: Update with new attributes. > * config/arm/fa526.md: Update with new attributes. > * config/arm/fa606te.md: Update with new attributes. > * config/arm/fa626te.md: Update with new attributes. > * config/arm/fa726te.md: Update with new attributes. > OK. R.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 96705862de6b53322828fd60df15207af4b2ed61..5aa127bcb47912f1986007d4491b865555e92c23 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4134,7 +4134,7 @@ (define_insn "aarch64_load_tp_hard" "" "mrs\\t%0, tpidr_el0" [(set_attr "v8type" "mrs") - (set_attr "type" "mov_reg") + (set_attr "type" "mrs") (set_attr "mode" "DI")] ) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index fd0b1cbdccd23ad4d18be50417c7532b29840b91..8a482b570ec039aad888d7d7d902b48f7e453abc 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12453,7 +12453,7 @@ (define_insn "load_tp_hard" "TARGET_HARD_TP" "mrc%?\\tp15, 0, %0, c13, c0, 3\\t@ load_tp_hard" [(set_attr "predicable" "yes") - (set_attr "type" "mov_reg")] + (set_attr "type" "mrs")] ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 6b1559260246a11e6d74f7f467dbeae761d934ea..ccad62076089b5e095f472fdbf298ba7226ae4ec 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -68,7 +68,7 @@ (define_insn_reservation "cortex_a15_alu shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)") ;; ALU ops with immediate shift diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index fa3e9d59c91028214ca7aa1be2c6668b4af5e6d3..22e0a08f38e7620cef745d28c5373e2daf957f7d 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -64,7 +64,7 @@ (define_insn_reservation "cortex_a5_alu" adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a5_ex1") (define_insn_reservation "cortex_a5_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 33b5ca30150fc57e7a3c4886c01b9e8092fc3ffa..48d0d03853f147d2d7cc15c1208304617b9c1ec4 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -73,7 +73,7 @@ (define_insn_reservation "cortex_a53_alu adr,bfm,csel,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a53_slot_any") (define_insn_reservation "cortex_a53_alu_shift" 2 diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index ba9da8046ebd4a886c425238ab28df5ab9d85a8a..a72a88d90af1c5491115ee84af47ec6d4f593535 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -110,7 +110,7 @@ (define_insn_reservation "cortex_a7_alu_ logic_shift_reg,logics_shift_reg,\ mov_shift,mov_shift_reg,\ mvn_shift,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a7_ex1") ;; Forwarding path for unshifted operands. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index ed0b351365c8ef363fbecf476e23f25c4e17cc08..1eade5e124400e9241ae1909f417f3030d8b939f 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -111,7 +111,8 @@ (define_insn_reservation "cortex_a8_alu_ (define_insn_reservation "cortex_a8_mov" 1 (and (eq_attr "tune" "cortexa8") (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\ - mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")) + mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ + mrs")) "cortex_a8_default") ;; Exceptions to the default latencies for data processing instructions. diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index dd7505a0cf54cd288c5e7cea675017bab4be9ba4..7c62d8489aeb08c5da9b0a008421a90c70ba5172 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -87,7 +87,7 @@ (define_insn_reservation "cortex_a9_dp" shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_shift_reg,mov_shift,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_a9_p0_default|cortex_a9_p1_default") ;; An instruction using the shifter will go down E1. diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 8663eb77fa109b8cec20aa20e2392829a947c833..9ae4cc3143b3c96612b0ab886031362feabfbc19 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -42,7 +42,7 @@ (define_insn_reservation "cortex_m4_alu" logic_shift_reg,logics_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ - multiple,no_insn") + mrs,multiple,no_insn") (ior (eq_attr "mul32" "yes") (eq_attr "mul64" "yes")))) "cortex_m4_ex") diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index 11a6e6419f53eba692b418870467f0ae7d6b2d32..7a3ceeb15d7208c20b8dc8b791f62426afa49907 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -102,7 +102,7 @@ (define_insn_reservation "cortex_r4_alu_ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\ logic_shift_reg,logics_shift_reg,\ mov_shift_reg,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "cortex_r4_alu_shift_reg") ;; An ALU instruction followed by an ALU instruction with no early dep. diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index ddd48fe107e49e4dbf6f0614081dd54910698810..401abd3c0a03d516d1c8baf67bde768882050e28 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -68,7 +68,7 @@ (define_insn_reservation "526_alu_op" 1 adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa526_core") (define_insn_reservation "526_alu_shift_op" 2 diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 892ea31fccd92629f9699cf98ddda8c70789d0fd..88347bc2d96c10fdace2f69caea1d2c2a6729875 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -73,7 +73,7 @@ (define_insn_reservation "606te_alu_op" logic_shift_reg,logics_shift_reg,\ mov_imm,mov_reg,mov_shift,mov_shift_reg,\ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa606te_core") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 8b9253171d4db7114bb878f7f82e9a5aced9d8ef..e6790a2121593f3a0ab08bb41c2506712be4e001 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -74,7 +74,7 @@ (define_insn_reservation "626te_alu_op" adr,bfm,rev,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa626te_core") (define_insn_reservation "626te_alu_shift_op" 2 diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 28be92de75a91910fad526f4d948f9a3857e77ec..d0a03981eec7fab412ed581f80f5803bd2e711a3 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -91,7 +91,7 @@ (define_insn_reservation "726te_alu_op" adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ - multiple,no_insn")) + mrs,multiple,no_insn")) "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") ;; ALU operations with a shift-by-register operand. diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 6c2db277dca7ff9e34db0e945f5114aaa0994202..7a96438fd48d5e52dda4508ed637695c8290f492 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -106,6 +106,7 @@ ; register. This includes MOVW, but not MOVT. ; mov_shift simple MOV instruction, shifted operand by a constant. ; mov_shift_reg simple MOV instruction, shifted operand by a register. +; mrs system/special/co-processor register move. ; mul integer multiply. ; muls integer multiply, flag setting. ; multiple more than one instruction, candidate for future @@ -372,6 +373,7 @@ (define_attr "type" mov_reg,\ mov_shift,\ mov_shift_reg,\ + mrs,\ mul,\ muls,\ multiple,\