@@ -906,7 +906,7 @@ (define_insn "*movti_aarch64"
str\\t%q1, %0"
[(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \
load2,store2,store2,fpsimd_load,fpsimd_store")
- (set_attr "type" "mov_reg,f_mcr,f_mrc,*, \
+ (set_attr "type" "multiple,f_mcr,f_mrc,*, \
load2,store2,store2,f_loadd,f_stored")
(set_attr "simd_type" "*,*,*,simd_move,*,*,*,*,*")
(set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI")
@@ -1024,7 +1024,7 @@ (define_insn "*movtf_aarch64"
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
- (set_attr "type" "logic_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
+ (set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,f_loadd,f_stored")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
@@ -6141,7 +6141,7 @@ (define_insn "*thumb1_movdi_insn"
}
}"
[(set_attr "length" "4,4,6,2,2,6,4,4")
- (set_attr "type" "multiple,mov_reg,multiple,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,multiple,multiple,load2,store2,load2,store2,multiple")
(set_attr "pool_range" "*,*,*,*,*,1018,*,*")]
)
@@ -7221,7 +7221,7 @@ (define_insn "*arm32_movhf"
}
"
[(set_attr "conds" "unconditional")
- (set_attr "type" "load1,store1,mov_reg,mov_reg")
+ (set_attr "type" "load1,store1,mov_reg,multiple")
(set_attr "length" "4,4,4,8")
(set_attr "predicable" "yes")]
)
@@ -7466,7 +7466,7 @@ (define_insn "*thumb_movdf_insn"
}
"
[(set_attr "length" "4,2,2,6,4,4")
- (set_attr "type" "multiple,load2,store2,load2,store2,mov_reg")
+ (set_attr "type" "multiple,load2,store2,load2,store2,multiple")
(set_attr "pool_range" "*,*,*,1018,*,*")]
)