Message ID | 1375791531-31014-4-git-send-email-taras@ti.com |
---|---|
State | Accepted |
Delegated to: | Tom Rini |
Headers | show |
Hi Taras, On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote: > From: Lubomir Popov <lpopov@mm-sol.com> > > OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. > This memory has 4Gb x 2CS = 8Gb configuration. > Add configuration for runtime calculation and precalculated cases. > > Patch is based on a draft Lubomir's patch [1]. > > [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? Rest looks fine to me. Thanks and regards, Lokesh > > Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> > [taras@ti.com: cleaned up patch and fixed precalculated values] > Signed-off-by: Taras Kondratiuk <taras@ti.com> @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; > --- > arch/arm/cpu/armv7/omap4/sdram_elpida.c | 41 +++++++++++++++++++++++++------ > 1 file changed, 34 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c > index d76dde7..67a7926 100644 > --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c > +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c > @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { > .emif_ddr_phy_ctlr_1 = 0x049ff418 > }; > > +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { > + .sdram_config_init = 0x80800eb2, > + .sdram_config = 0x80801ab2, > + .ref_ctrl = 0x00000618, > + .sdram_tim1 = 0x10eb0662, > + .sdram_tim2 = 0x20370dd2, > + .sdram_tim3 = 0x00b1c33f, > + .read_idle_ctrl = 0x000501ff, > + .zq_config = 0x500b3215, > + .temp_alert_config = 0x58016893, > + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, > + .emif_ddr_phy_ctlr_1 = 0x049ff418 > +}; > + > const struct emif_regs emif_regs_elpida_400_mhz_2cs = { > .sdram_config_init = 0x80000eb9, > .sdram_config = 0x80001ab9, > @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) > *regs = &emif_regs_elpida_380_mhz_1cs; > else if (omap4_rev == OMAP4430_ES2_0) > *regs = &emif_regs_elpida_200_mhz_2cs; > - else > + else if (omap4_rev < OMAP4470_ES1_0) > *regs = &emif_regs_elpida_400_mhz_2cs; > + else > + *regs = &emif_regs_elpida_400_mhz_1cs; > } > void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) > __attribute__((weak, alias("emif_get_reg_dump_sdp"))); > @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { > .manufacturer = LPDDR2_MANUFACTURER_ELPIDA > }; > > +static const struct lpddr2_device_details elpida_4G_S4_details = { > + .type = LPDDR2_TYPE_S4, > + .density = LPDDR2_DENSITY_4Gb, @@ -138,6 +138,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; > + .io_width = LPDDR2_IO_WIDTH_32, > + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA > +}; > + > struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, > struct lpddr2_device_details *lpddr2_dev_details) > { > u32 omap_rev = omap_revision(); > > /* EMIF1 & EMIF2 have identical configuration */ > - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { > - /* Nothing connected on CS1 for ES1.0 */ > + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) > + && (cs == CS1)) { > + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ > return NULL; > - } else { > - /* In all other cases Elpida 2G device */ > + } else if (omap_rev < OMAP4470_ES1_0) { > + /* In all other 4430/4460 cases Elpida 2G device */ > *lpddr2_dev_details = elpida_2G_S4_details; > - return lpddr2_dev_details; > + } else { > + /* 4470: 4G device */ > + *lpddr2_dev_details = elpida_4G_S4_details; > } > + return lpddr2_dev_details; > } > > struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, > @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, > /* Identical devices on EMIF1 & EMIF2 */ > *cs0_device_timings = &elpida_2G_S4_timings; > > - if (omap_rev == OMAP4430_ES1_0) > + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) > *cs1_device_timings = NULL; > else > *cs1_device_timings = &elpida_2G_S4_timings; >
On 08/06/2013 05:21 PM, Lokesh Vutla wrote: > Hi Taras, > On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote: >> From: Lubomir Popov <lpopov@mm-sol.com> >> >> OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. >> This memory has 4Gb x 2CS = 8Gb configuration. >> Add configuration for runtime calculation and precalculated cases. >> >> Patch is based on a draft Lubomir's patch [1]. >> >> [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html > Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? > Rest looks fine to me. If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works. The only minor issue is that detection is called twice during boot: for dmm_init() and for do_sdram_init(). In case you need additional details I've put boot log with debug enabled below. U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) OMAP4470 ES1.0 >>sdram_init() in_sdram = 0 get_mr: EMIF1 cs 0 mr 00000000 val 0x0 get_mr: EMIF1 cs 0 mr 00000004 val 0x3 get_mr: EMIF1 cs 0 mr 00000005 val 0x3 get_mr: EMIF1 cs 0 mr 00000006 val 0x0 get_mr: EMIF1 cs 0 mr 00000007 val 0x0 get_mr: EMIF1 cs 0 mr 00000008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 80000000 val 0x3 get_mr: EMIF2 cs 0 mr 00000000 val 0x0 get_mr: EMIF2 cs 0 mr 00000004 val 0x3 get_mr: EMIF2 cs 0 mr 00000005 val 0x3 get_mr: EMIF2 cs 0 mr 00000006 val 0x0 get_mr: EMIF2 cs 0 mr 00000007 val 0x0 get_mr: EMIF2 cs 0 mr 00000008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif1_size 0x20000000 emif2_size 0x20000000 >>do_sdram_init() 4c000000 get_mr: EMIF1 cs 0 mr 00000000 val 0x0 get_mr: EMIF1 cs 0 mr 00000004 val 0x3 get_mr: EMIF1 cs 0 mr 00000005 val 0x3 get_mr: EMIF1 cs 0 mr 00000006 val 0x0 get_mr: EMIF1 cs 0 mr 00000007 val 0x0 get_mr: EMIF1 cs 0 mr 00000008 val 0x18 EMIF1 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF1 cs 1 mr 80000000 val 0x3 emif: timings table: 400000000 emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 get_mr: EMIF1 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4c000000 >>do_sdram_init() 4d000000 get_mr: EMIF2 cs 0 mr 00000000 val 0x0 get_mr: EMIF2 cs 0 mr 00000004 val 0x3 get_mr: EMIF2 cs 0 mr 00000005 val 0x3 get_mr: EMIF2 cs 0 mr 00000006 val 0x0 get_mr: EMIF2 cs 0 mr 00000007 val 0x0 get_mr: EMIF2 cs 0 mr 00000008 val 0x18 EMIF2 CS0 Elpida LPDDR2-S4 512 MB get_mr: EMIF2 cs 1 mr 80000000 val 0x3 emif: timings table: 400000000 emif: addressing table index 6 regs->sdram_config_init - 0x80000eb2 regs->sdram_config - 0x80001ab2 regs->ref_ctrl - 0x00000618 regs->sdram_tim1 - 0x10eb0662 regs->sdram_tim2 - 0x20370dd2 regs->sdram_tim3 - 0x00b1c33f regs->read_idle_ctrl - 0x000501ff regs->temp_alert_config - 0x58016893 regs->zq_config - 0x500b3214 regs->emif_ddr_phy_ctlr_1 - 0x049ff418 regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 get_mr: EMIF2 cs 0 mr 00000000 val 0x0 <<do_sdram_init() 4d000000 get_ram_size() successful<<sdram_init() OMAP SD/MMC: 0 reading u-boot.img reading u-boot.img
Hi, On Tuesday 06 August 2013 09:27 PM, Taras Kondratiuk wrote: > On 08/06/2013 05:21 PM, Lokesh Vutla wrote: >> Hi Taras, >> On Tuesday 06 August 2013 05:48 PM, Taras Kondratiuk wrote: >>> From: Lubomir Popov <lpopov@mm-sol.com> >>> >>> OMAP4470 SDP SoM has EDB8164B3PF PoP memory on board. >>> This memory has 4Gb x 2CS = 8Gb configuration. >>> Add configuration for runtime calculation and precalculated cases. >>> >>> Patch is based on a draft Lubomir's patch [1]. >>> >>> [1] http://lists.denx.de/pipermail/u-boot/2013-April/150851.html >> Just curious to know, Have you tried SDRAM_AUTO_DETECTION ? >> Rest looks fine to me. > > If you mean SYS_AUTOMATIC_SDRAM_DETECTION then yes I've tried it and it works. Cool, thats fine...!! Thanks and regards, Lokesh > The only minor issue is that detection is called twice during boot: > for dmm_init() and for do_sdram_init(). > > In case you need additional details I've put boot log with debug enabled below. > > U-Boot SPL 2013.07-00116-gd7325e5-dirty (Aug 06 2013 - 18:20:56) > OMAP4470 ES1.0 >>>sdram_init() > in_sdram = 0 > get_mr: EMIF1 cs 0 mr 00000000 val 0x0 > get_mr: EMIF1 cs 0 mr 00000004 val 0x3 > get_mr: EMIF1 cs 0 mr 00000005 val 0x3 > get_mr: EMIF1 cs 0 mr 00000006 val 0x0 > get_mr: EMIF1 cs 0 mr 00000007 val 0x0 > get_mr: EMIF1 cs 0 mr 00000008 val 0x18 > EMIF1 CS0 Elpida LPDDR2-S4 512 MB > get_mr: EMIF1 cs 1 mr 80000000 val 0x3 > get_mr: EMIF2 cs 0 mr 00000000 val 0x0 > get_mr: EMIF2 cs 0 mr 00000004 val 0x3 > get_mr: EMIF2 cs 0 mr 00000005 val 0x3 > get_mr: EMIF2 cs 0 mr 00000006 val 0x0 > get_mr: EMIF2 cs 0 mr 00000007 val 0x0 > get_mr: EMIF2 cs 0 mr 00000008 val 0x18 > EMIF2 CS0 Elpida LPDDR2-S4 512 MB > get_mr: EMIF2 cs 1 mr 80000000 val 0x3 > emif1_size 0x20000000 emif2_size 0x20000000 >>>do_sdram_init() 4c000000 > get_mr: EMIF1 cs 0 mr 00000000 val 0x0 > get_mr: EMIF1 cs 0 mr 00000004 val 0x3 > get_mr: EMIF1 cs 0 mr 00000005 val 0x3 > get_mr: EMIF1 cs 0 mr 00000006 val 0x0 > get_mr: EMIF1 cs 0 mr 00000007 val 0x0 > get_mr: EMIF1 cs 0 mr 00000008 val 0x18 > EMIF1 CS0 Elpida LPDDR2-S4 512 MB > get_mr: EMIF1 cs 1 mr 80000000 val 0x3 > emif: timings table: 400000000 > emif: addressing table index 6 > regs->sdram_config_init - 0x80000eb2 > regs->sdram_config - 0x80001ab2 > regs->ref_ctrl - 0x00000618 > regs->sdram_tim1 - 0x10eb0662 > regs->sdram_tim2 - 0x20370dd2 > regs->sdram_tim3 - 0x00b1c33f > regs->read_idle_ctrl - 0x000501ff > regs->temp_alert_config - 0x58016893 > regs->zq_config - 0x500b3214 > regs->emif_ddr_phy_ctlr_1 - 0x049ff418 > regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 > get_mr: EMIF1 cs 0 mr 00000000 val 0x0 > <<do_sdram_init() 4c000000 >>>do_sdram_init() 4d000000 > get_mr: EMIF2 cs 0 mr 00000000 val 0x0 > get_mr: EMIF2 cs 0 mr 00000004 val 0x3 > get_mr: EMIF2 cs 0 mr 00000005 val 0x3 > get_mr: EMIF2 cs 0 mr 00000006 val 0x0 > get_mr: EMIF2 cs 0 mr 00000007 val 0x0 > get_mr: EMIF2 cs 0 mr 00000008 val 0x18 > EMIF2 CS0 Elpida LPDDR2-S4 512 MB > get_mr: EMIF2 cs 1 mr 80000000 val 0x3 > emif: timings table: 400000000 > emif: addressing table index 6 > regs->sdram_config_init - 0x80000eb2 > regs->sdram_config - 0x80001ab2 > regs->ref_ctrl - 0x00000618 > regs->sdram_tim1 - 0x10eb0662 > regs->sdram_tim2 - 0x20370dd2 > regs->sdram_tim3 - 0x00b1c33f > regs->read_idle_ctrl - 0x000501ff > regs->temp_alert_config - 0x58016893 > regs->zq_config - 0x500b3214 > regs->emif_ddr_phy_ctlr_1 - 0x049ff418 > regs->emif_ddr_phy_ctlr_1_init - 0x049ffff5 > get_mr: EMIF2 cs 0 mr 00000000 val 0x0 > <<do_sdram_init() 4d000000 > get_ram_size() successful<<sdram_init() > OMAP SD/MMC: 0 > reading u-boot.img > reading u-boot.img >
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index d76dde7..67a7926 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -60,6 +60,20 @@ static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, @@ -107,8 +121,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,20 +154,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA }; +static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision(); /* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; } struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -265,7 +292,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings; - if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings;