Message ID | 1375798175-15169-1-git-send-email-clsee@altera.com |
---|---|
State | Superseded |
Delegated to: | Albert ARIBAUD |
Headers | show |
On Tue, 2013-08-06 at 09:09 -0500, Chin Liang See wrote: > Consolidating reset code into reset_manager.c. > Also separating reset configuration for virtual target > and real hardware Cyclone V development kit > > Signed-off-by: Chin Liang See <clsee@altera.com> > Reviewed-by: Pavel Machek Add Pavel's email address. > Cc: Wolfgang Denk <wd@denx.de> > CC: Pavel Machek <pavel@denx.de> > Cc: Dinh Nguyen <dinguyen@altera.com> > Cc: Tom Rini <trini@ti.com> > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > --- > Changes for v2: > - Fixed the long subject of the patch > - Consolidated the reset_manager structure between virtual target and dev kit > Changes for v3: > - Added change log for each revision change > - Removed the < > between the date of copyright header > Changes for v4: > - Updated the license header for reset_manager.c > Changes for v5: > - Updated the license header for reset_manager.c to SPDX re-org to have latest changes, v5, at the top. > --- > arch/arm/cpu/armv7/socfpga/Makefile | 2 +- > arch/arm/cpu/armv7/socfpga/misc.c | 27 -------------- > arch/arm/cpu/armv7/socfpga/reset_manager.c | 40 +++++++++++++++++++++ > arch/arm/include/asm/arch-socfpga/reset_manager.h | 10 ++++-- > 4 files changed, 48 insertions(+), 31 deletions(-) > create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c > > diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile > index 3b48ac9..5024fc5 100644 > --- a/arch/arm/cpu/armv7/socfpga/Makefile > +++ b/arch/arm/cpu/armv7/socfpga/Makefile > @@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk > LIB = $(obj)lib$(SOC).o > > SOBJS := lowlevel_init.o > -COBJS-y := misc.o timer.o > +COBJS-y := misc.o timer.o reset_manager.o > COBJS-$(CONFIG_SPL_BUILD) += spl.o > > COBJS := $(COBJS-y) > diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c > index 66edb3c..2f1c716 100644 > --- a/arch/arm/cpu/armv7/socfpga/misc.c > +++ b/arch/arm/cpu/armv7/socfpga/misc.c > @@ -6,36 +6,9 @@ > > #include <common.h> > #include <asm/io.h> > -#include <asm/arch/reset_manager.h> > > DECLARE_GLOBAL_DATA_PTR; > > -static const struct socfpga_reset_manager *reset_manager_base = > - (void *)SOCFPGA_RSTMGR_ADDRESS; > - > -/* > - * Write the reset manager register to cause reset > - */ > -void reset_cpu(ulong addr) > -{ > - /* request a warm reset */ > - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); > - /* > - * infinite loop here as watchdog will trigger and reset > - * the processor > - */ > - while (1) > - ; > -} > - > -/* > - * Release peripherals from reset based on handoff > - */ > -void reset_deassert_peripherals_handoff(void) > -{ > - writel(0, &reset_manager_base->per_mod_reset); > -} > - > int dram_init(void) > { > gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); > diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c > new file mode 100644 > index 0000000..2281743 > --- /dev/null > +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c > @@ -0,0 +1,40 @@ > +/* > + * Copyright Altera Corporation (C) 2013 > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/reset_manager.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static const struct socfpga_reset_manager *reset_manager_base = > + (void *)SOCFPGA_RSTMGR_ADDRESS; > + > +/* > + * Write the reset manager register to cause reset > + */ > +void reset_cpu(ulong addr) > +{ > + /* request a warm reset */ > + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), > + &reset_manager_base->ctrl); > + /* > + * infinite loop here as watchdog will trigger and reset > + * the processor > + */ > + while (1) > + ; > +} > + > +/* > + * Release peripherals from reset based on handoff > + */ > +void reset_deassert_peripherals_handoff(void) > +{ > + writel(0, &reset_manager_base->per_mod_reset); > +} > + > + > diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h > index 13d7357..3e95476 100644 > --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h > +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h > @@ -11,16 +11,20 @@ void reset_cpu(ulong addr); > void reset_deassert_peripherals_handoff(void); > > struct socfpga_reset_manager { > - u32 padding1; > + u32 status; > u32 ctrl; > - u32 padding2; > - u32 padding3; > + u32 counts; > + u32 padding1; > u32 mpu_mod_reset; > u32 per_mod_reset; > u32 per2_mod_reset; > u32 brg_mod_reset; > }; > > +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) > +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 > +#else > #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 > +#endif > > #endif /* _RESET_MANAGER_H_ */
On Tue, 2013-08-06 at 11:01 -0500, Dinh Nguyen wrote: > On Tue, 2013-08-06 at 09:09 -0500, Chin Liang See wrote: > > Consolidating reset code into reset_manager.c. > > Also separating reset configuration for virtual target > > and real hardware Cyclone V development kit > > > > Signed-off-by: Chin Liang See <clsee@altera.com> > > Reviewed-by: Pavel Machek > > Add Pavel's email address. Noted will fix in v6 > > > Cc: Wolfgang Denk <wd@denx.de> > > CC: Pavel Machek <pavel@denx.de> > > Cc: Dinh Nguyen <dinguyen@altera.com> > > Cc: Tom Rini <trini@ti.com> > > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > > --- > > Changes for v2: > > - Fixed the long subject of the patch > > - Consolidated the reset_manager structure between virtual target and dev kit > > Changes for v3: > > - Added change log for each revision change > > - Removed the < > between the date of copyright header > > Changes for v4: > > - Updated the license header for reset_manager.c > > Changes for v5: > > - Updated the license header for reset_manager.c to SPDX > > re-org to have latest changes, v5, at the top. Noted will fix in v6 Thanks Chin Liang
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 3b48ac9..5024fc5 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o +COBJS-y := misc.o timer.o reset_manager.o COBJS-$(CONFIG_SPL_BUILD) += spl.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 66edb3c..2f1c716 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -6,36 +6,9 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/reset_manager.h> DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 0000000..2281743 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,40 @@ +/* + * Copyright Altera Corporation (C) 2013 + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + + diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 13d7357..3e95476 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -11,16 +11,20 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); struct socfpga_reset_manager { - u32 padding1; + u32 status; u32 ctrl; - u32 padding2; - u32 padding3; + u32 counts; + u32 padding1; u32 mpu_mod_reset; u32 per_mod_reset; u32 per2_mod_reset; u32 brg_mod_reset; }; +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 +#else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#endif #endif /* _RESET_MANAGER_H_ */