| Message ID | 56EA75BA695AE044ACFB41322F6D2BF4022320D1@BADAG02.ba.imgtec.org |
|---|---|
| State | New |
| Headers | show |
On 06/17/2013 03:40 PM, Petar Jovanovic wrote: > From: Petar Jovanovic <petar.jovanovic@imgtec.com> > > Multiplication of Q15 fractional halfword vectors was incorrect in the > previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take > element signs into account. This change fixes it, and it adds a test case > for it. > > The change also removes unnecessary cast in the function > mipsdsp_mul_q15_q15_overflowflag21(). > > Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> > --- > target-mips/dsp_helper.c | 4 ++-- > tests/tcg/mips/mips32-dsp/mulq_rs_ph.c | 19 ++++++++++++++++++- > 2 files changed, 20 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
ping http://patchwork.ozlabs.org/patch/245990/
ping
ping
ping Can somebody submit these for 1.6? Thank you. Regards, Petar
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4116de9..c718a78 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -390,7 +390,7 @@ static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b, temp = 0x7FFFFFFF; set_DSPControl_overflow_flag(1, 21, env); } else { - temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1; + temp = ((int16_t)a * (int16_t)b) << 1; } return temp; @@ -622,7 +622,7 @@ static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b, temp = 0x7FFF0000; set_DSPControl_overflow_flag(1, 21, env); } else { - temp = (a * b) << 1; + temp = ((int16_t)a * (int16_t)b) << 1; temp = temp + 0x00008000; } diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c index c720603..370c2a8 100644 --- a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c +++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c @@ -12,7 +12,24 @@ int main() resultdsp = 1; __asm - ("mulq_rs.ph %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x80011234; + rt = 0x80024321; + result = 0x7FFD098C; + resultdsp = 0; + + __asm + ("wrdsp $0\n\t" + "mulq_rs.ph %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt)