| Message ID | 51D11DEF.8070302@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Michael Ellerman |
| Headers | show |
On Mon, Jul 01, 2013 at 11:43:03AM +0530, Anshuman Khandual wrote: > powerpc, perf: Add generic cache reference and cache miss events for POWER8 PMU > > This enables generic cache reference and cache miss events on POWER8 systems by > utilizing raw PMU event codes for L1 cache reference and L1 cache miss events > respectively. > > Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> > > diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c > index f7d1c4f..5ccddac 100644 > --- a/arch/powerpc/perf/power8-pmu.c > +++ b/arch/powerpc/perf/power8-pmu.c > @@ -24,6 +24,8 @@ > #define PM_INST_CMPL 0x00002 > #define PM_BRU_FIN 0x10068 > #define PM_BR_MPRED_CMPL 0x400f6 > +#define PM_LD_MISS_L1 0x3E054 > +#define PM_LD_REF_L1 0x100EE Hi Anshuman, Which system did you test this on and what results did you see? cheers
> Hi Anshuman, > > Which system did you test this on and what results did you see? > Tested this on a power8 system.
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c index f7d1c4f..5ccddac 100644 --- a/arch/powerpc/perf/power8-pmu.c +++ b/arch/powerpc/perf/power8-pmu.c @@ -24,6 +24,8 @@ #define PM_INST_CMPL 0x00002 #define PM_BRU_FIN 0x10068 #define PM_BR_MPRED_CMPL 0x400f6 +#define PM_LD_MISS_L1 0x3E054 +#define PM_LD_REF_L1 0x100EE /* @@ -518,6 +520,8 @@ static int power8_generic_events[] = { [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, + [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, + [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, }; static u64 power8_bhrb_filter_map(u64 branch_sample_type)
powerpc, perf: Add generic cache reference and cache miss events for POWER8 PMU This enables generic cache reference and cache miss events on POWER8 systems by utilizing raw PMU event codes for L1 cache reference and L1 cache miss events respectively. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>