diff mbox

[x86] Remove 2 builtins

Message ID alpine.DEB.2.02.1306092247030.24602@stedding.saclay.inria.fr
State New
Headers show

Commit Message

Marc Glisse June 9, 2013, 9:09 p.m. UTC 
Hello,

this patch removes 2 builtins that are undocumented, unused, and have 
confusing semantics. Bootstrap+testsuite on x86_64-linux-gnu.


2013-06-10  Marc Glisse  <marc.glisse@inria.fr>

 	PR target/57224
 	* config/i386/i386.c (enum ix86_builtins, bdesc_args): Remove
 	IX86_BUILTIN_CMPNGTSS and IX86_BUILTIN_CMPNGESS.

Comments

Marc Glisse June 26, 2013, 2:22 p.m. UTC | #1 
Ping http://gcc.gnu.org/ml/gcc-patches/2013-06/msg00478.html

On Sun, 9 Jun 2013, Marc Glisse wrote:

> Hello,
>
> this patch removes 2 builtins that are undocumented, unused, and have 
> confusing semantics. Bootstrap+testsuite on x86_64-linux-gnu.
>
>
> 2013-06-10  Marc Glisse  <marc.glisse@inria.fr>
>
> 	PR target/57224
> 	* config/i386/i386.c (enum ix86_builtins, bdesc_args): Remove
> 	IX86_BUILTIN_CMPNGTSS and IX86_BUILTIN_CMPNGESS.
>
>
Richard Henderson June 27, 2013, 7:40 p.m. UTC | #2 
On 06/26/2013 07:22 AM, Marc Glisse wrote:
> Ping http://gcc.gnu.org/ml/gcc-patches/2013-06/msg00478.html
> 
> On Sun, 9 Jun 2013, Marc Glisse wrote:
> 
>> Hello,
>>
>> this patch removes 2 builtins that are undocumented, unused, and have
>> confusing semantics. Bootstrap+testsuite on x86_64-linux-gnu.
>>
>>
>> 2013-06-10  Marc Glisse  <marc.glisse@inria.fr>
>>
>>     PR target/57224
>>     * config/i386/i386.c (enum ix86_builtins, bdesc_args): Remove
>>     IX86_BUILTIN_CMPNGTSS and IX86_BUILTIN_CMPNGESS.
>>
>>
> 

Ok.


r~
diff mbox

Patch

Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 199867)
+++ config/i386/i386.c	(working copy)
@@ -25903,22 +25903,20 @@  enum ix86_builtins
   IX86_BUILTIN_CMPNGTPS,
   IX86_BUILTIN_CMPNGEPS,
   IX86_BUILTIN_CMPORDPS,
   IX86_BUILTIN_CMPUNORDPS,
   IX86_BUILTIN_CMPEQSS,
   IX86_BUILTIN_CMPLTSS,
   IX86_BUILTIN_CMPLESS,
   IX86_BUILTIN_CMPNEQSS,
   IX86_BUILTIN_CMPNLTSS,
   IX86_BUILTIN_CMPNLESS,
-  IX86_BUILTIN_CMPNGTSS,
-  IX86_BUILTIN_CMPNGESS,
   IX86_BUILTIN_CMPORDSS,
   IX86_BUILTIN_CMPUNORDSS,
 
   IX86_BUILTIN_COMIEQSS,
   IX86_BUILTIN_COMILTSS,
   IX86_BUILTIN_COMILESS,
   IX86_BUILTIN_COMIGTSS,
   IX86_BUILTIN_COMIGESS,
   IX86_BUILTIN_COMINEQSS,
   IX86_BUILTIN_UCOMIEQSS,
@@ -27541,22 +27539,20 @@  static const struct builtin_description
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
-  { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
-  { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
 
   { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
 
   { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3,  "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
   { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },