[U-Boot,3/4] ARM: AM33xx: Move s_init to a common place

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 1d743d6..3d08673 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -145,7 +145,7 @@  int arch_misc_init(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
-void rtc32k_enable(void)
+static void rtc32k_enable(void)
 {
 	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
@@ -161,11 +161,7 @@  void rtc32k_enable(void)
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
 
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
 {
 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 	u32 regval;
@@ -182,4 +178,42 @@  void uart_soft_reset(void)
 	regval |= UART_SMART_IDLE_EN;
 	writel(regval, &uart_base->uartsyscfg);
 }
+
+static void watchdog_disable(void)
+{
+	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
 #endif
+
+void s_init(void)
+{
+	/*
+	 * Save the boot parameters passed from romcode.
+	 * We cannot delay the saving further than this,
+	 * to prevent overwrites.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	save_omap_boot_params();
+	watchdog_disable();
+	timer_init();
+	set_uart_mux_conf();
+	setup_clocks_for_console();
+	uart_soft_reset();
+
+	gd = &gdata;
+	preloader_console_init();
+
+	prcm_init();
+	set_mux_conf_regs();
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+	sdram_init();
+#endif
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index 1a23746..ca7d7ad 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -285,6 +285,12 @@  static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
 	while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
 		;
+
+	/* RTC clocks */
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
+	writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
+	while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
+		;
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 47d3dee..3abb609 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,8 +44,6 @@  void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static struct dmm_lisa_map_regs *hw_lisa_map_regs =
-				(struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
 				(struct vtp_reg *)VTP0_CTRL_ADDR,
 				(struct vtp_reg *)VTP1_CTRL_ADDR};
@@ -53,6 +51,9 @@  static struct vtp_reg *vtpreg[2] = {
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
 
+#ifdef CONFIG_TI81XX
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
 void config_dmm(const struct dmm_lisa_map_regs *regs)
 {
 	enable_dmm_clocks();
@@ -67,6 +68,7 @@  void config_dmm(const struct dmm_lisa_map_regs *regs)
 	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
 	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
 }
+#endif
 
 static void config_vtp(int nr)
 {
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 89b63d9..dc49e7e 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -24,8 +24,10 @@ 
 #define CONFIG_SYS_MPUCLK	550
 #endif
 
-extern void pll_init(void);
-extern void enable_emif_clocks(void);
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
 extern void enable_dmm_clocks(void);
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 04b8561..4efa1c2 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -43,7 +43,8 @@  void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
 
-void rtc32k_enable(void);
-void uart_soft_reset(void);
+void set_uart_mux_conf(void);
+void set_mux_conf_regs(void);
+void sdram_init(void);
 u32 wait_on_value(u32, u32, void *, u32);
 #endif
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index fe80084..809448f 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -35,8 +35,6 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define RMII_MODE_ENABLE	0x4D
 
@@ -74,54 +72,23 @@  static struct emif_regs ddr3_emif_reg_data = {
 	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 };
-#endif
 
-/*
- * Early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	setup_clocks_for_console();
-
 	enable_uart0_pin_mux();
+}
 
-	uart_soft_reset();
-	gd = &gdata;
-
-	preloader_console_init();
-
-	prcm_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
-	/* Configure board pin mux */
+void set_mux_conf_regs(void)
+{
 	enable_board_pin_mux();
+}
 
+void sdram_init(void)
+{
 	config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
 		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 0cca8d7..0d6a64c 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -38,8 +38,6 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
 #define RGMII_MODE_ENABLE	0xA
@@ -84,57 +82,27 @@  static struct emif_regs ddr3_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
-#endif
 
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/*
-	 * WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
 	enable_uart0_pin_mux();
-	uart_soft_reset();
-
-	gd = &gdata;
-
-	preloader_console_init();
+}
 
+void set_mux_conf_regs(void)
+{
 	/* Initalize the board header */
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	enable_board_pin_mux();
+}
 
+void sdram_init(void)
+{
 	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
 			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index bebfa60..3b50dd0 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -37,8 +37,6 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
 #define RGMII_MODE_ENABLE	0x3A
@@ -282,36 +280,8 @@  int spl_start_uboot(void)
 }
 #endif
 
-#endif
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	setup_clocks_for_console();
-
 #ifdef CONFIG_SERIAL1
 	enable_uart0_pin_mux();
 #endif /* CONFIG_SERIAL1 */
@@ -330,25 +300,21 @@  void s_init(void)
 #ifdef CONFIG_SERIAL6
 	enable_uart5_pin_mux();
 #endif /* CONFIG_SERIAL6 */
+}
 
-	uart_soft_reset();
-
-	gd = &gdata;
-
-	preloader_console_init();
-
-	prcm_init();
-
+void set_mux_conf_regs(void)
+{
 	/* Initalize the board header */
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	if (read_eeprom() < 0)
 		puts("Could not get board ID.\n");
 
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
 	enable_board_pin_mux(&header);
+}
+
+void sdram_init(void)
+{
 	if (board_is_evm_sk()) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@@ -372,8 +338,8 @@  void s_init(void)
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 704fdf4..28d2561 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -35,30 +35,10 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SPL_BUILD
-static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#endif
-
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-static void uart_enable(void)
-{
-	/* UART softreset */
-	uart_soft_reset();
-}
-
-static void wdt_disable(void)
-{
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-}
-
 static const struct cmd_control evm_ddr2_cctrl_data = {
 	.cmd0csratio	= 0x80,
 	.cmd0dldiff	= 0x04,
@@ -108,63 +88,32 @@  static const struct ddr_data evm_ddr2_data = {
 	.datauserank0delay	= 1,
 	.datadldiff0		= 0x4,
 };
-#endif
 
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
+void set_uart_mux_conf(void)
 {
-#ifdef CONFIG_SPL_BUILD
-	/*
-	 * Save the boot parameters passed from romcode.
-	 * We cannot delay the saving further than this,
-	 * to prevent overwrites.
-	 */
-#ifdef CONFIG_SPL_BUILD
-	save_omap_boot_params();
-#endif
-
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	wdt_disable();
-
-	/* Enable timer */
-	timer_init();
-
-	setup_clocks_for_console();
-
 	/* Set UART pins */
 	enable_uart0_pin_mux();
+}
 
+void set_mux_conf_regs(void)
+{
 	/* Set MMC pins */
 	enable_mmc1_pin_mux();
 
 	/* Set Ethernet pins */
 	enable_enet_pin_mux();
+}
 
-	/* Enable UART */
-	uart_enable();
-
-	gd = &gdata;
-
-	preloader_console_init();
-
-	/* Setup the PLLs and the clocks for the peripherals */
-	prcm_init();
-
-	/* Enable RTC32K clock */
-	rtc32k_enable();
-
+void sdram_init(void)
+{
 	config_dmm(&evm_lisa_map_regs);
 
 	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif0_regs, 0);
 	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
 		   &evm_ddr2_emif1_regs, 1);
-#endif
 }
+#endif
 
 /*
  * Basic board specific setup.  Pinmux has been handled already.