| Message ID | 1370372252-4332-3-git-send-email-jagarwal@nvidia.com |
|---|---|
| State | Not Applicable |
| Headers | show |
On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote: [...] > @@ -29,7 +29,7 @@ > ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ > 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ > 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ > - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ > + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ > 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ > 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ That increases the I/O region size from 64 KiB to 1 MiB. Why is that necessary? I/O operations can only address 64 KiB, so I don't think adding more makes any sense. Thierry
> On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote: > [...] > > @@ -29,7 +29,7 @@ > > ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 > /* port 0 configuration space */ > > 0x82000000 0 0x00001000 0x00001000 0 0x00001000 > /* port 1 configuration space */ > > 0x82000000 0 0x00004000 0x00004000 0 0x00001000 > /* port 2 configuration space */ > > - 0x81000000 0 0 0x02000000 0 0x00010000 /* > downstream I/O */ > > + 0x81000000 0 0 0x02000000 0 0x00100000 /* > downstream I/O */ > > 0x82000000 0 0x20000000 0x20000000 0 0x10000000 > /* non-prefetchable memory */ > > 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; > /* > > prefetchable memory */ > > That increases the I/O region size from 64 KiB to 1 MiB. Why is that > necessary? I/O operations can only address 64 KiB, so I don't think adding > more makes any sense. > Okay, you can keep it 64KiB then, I did it to match with downstream. Please let me know if you want me to upload new patch for this or you will take care while integrating. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jun 10, 2013 at 09:55:12PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote: > [...] > > @@ -29,7 +29,7 @@ > > ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ > > 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ > > 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ > > - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ > > + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ > > 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ > > 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ > > That increases the I/O region size from 64 KiB to 1 MiB. Why is that > necessary? I/O operations can only address 64 KiB, so I don't think > adding more makes any sense. At least PCI allows 32bit I/O addresses. No idea if anyone uses them though. Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jun 11, 2013 at 10:30:48AM +0300, Peter De Schrijver wrote: > On Mon, Jun 10, 2013 at 09:55:12PM +0200, Thierry Reding wrote: > > * PGP Signed by an unknown key > > > > On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote: > > [...] > > > @@ -29,7 +29,7 @@ > > > ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ > > > 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ > > > 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ > > > - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ > > > + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ > > > 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ > > > 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ > > > > That increases the I/O region size from 64 KiB to 1 MiB. Why is that > > necessary? I/O operations can only address 64 KiB, so I don't think > > adding more makes any sense. > > At least PCI allows 32bit I/O addresses. No idea if anyone uses them though. I just realized that we are constrained to 64 KiB by the implementation of pci_ioremap_io(), which assumes each mapping is 64 KiB. Not that it couldn't be changed, but unless there actually is a use-case where more than 64 KiB are required I don't think we should worry about it. Thierry
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index a242b2e..a301389 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -21,7 +21,7 @@ reg-names = "pads", "afi", "cs"; interrupts = <0 98 0x04 /* controller interrupt */ 0 99 0x04>; /* MSI interrupt */ - + interrupt-names = "intr", "msi"; bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; @@ -29,7 +29,7 @@ ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */
- Add interrupt-names property - Correct downstream I/O size Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> --- Patch is based on remotes/gitorious_thierryreding_linux/tegra/next and should be applied on top of this. Changes in V3: - Avoided changes in cml clock as per review comment arch/arm/boot/dts/tegra30.dtsi | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)