@@ -739,7 +739,17 @@
;;
mips*-*-linux*) # Linux MIPS, either endian.
extra_parts="$extra_parts crtfastmath.o"
- tmake_file="${tmake_file} t-crtfm mips/t-mips16"
+ tmake_file="${tmake_file} t-crtfm"
+ # Check for MicroMIPS support.
+ case ${host} in
+ mips64r5900* | mipsr5900*)
+ # MicroMIPS uses floating point instructions
+ # which are not supported on r5900.
+ ;;
+ *)
+ tmake_file="${tmake_file} mips/t-mips16"
+ ;;
+ esac
md_unwind_header=mips/linux-unwind.h
if test "${ac_cv_sizeof_long_double}" = 16; then
tmake_file="${tmake_file} mips/t-tpbit"
@@ -777,10 +787,18 @@
tmake_file="$tmake_file mips/t-elf mips/t-crtstuff mips/t-mips16"
extra_parts="$extra_parts crti.o crtn.o"
;;
+mipsr5900-*-elf* | mipsr5900el-*-elf*)
+ tmake_file="$tmake_file mips/t-elf mips/t-crtstuff"
+ extra_parts="$extra_parts crti.o crtn.o"
+ ;;
mips64-*-elf* | mips64el-*-elf*)
tmake_file="$tmake_file mips/t-elf mips/t-crtstuff mips/t-mips16"
extra_parts="$extra_parts crti.o crtn.o"
;;
+mips64r5900-*-elf* | mips64r5900el-*-elf*)
+ tmake_file="$tmake_file mips/t-elf mips/t-crtstuff"
+ extra_parts="$extra_parts crti.o crtn.o"
+ ;;
mips64vr-*-elf* | mips64vrel-*-elf*)
tmake_file="$tmake_file mips/t-elf mips/t-vr mips/t-crtstuff"
extra_parts="$extra_parts crti.o crtn.o"
@@ -1937,10 +1937,16 @@
target_cpu_default="MASK_64BIT|MASK_FLOAT64"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64"
;;
-mips-*-elf* | mipsel-*-elf*)
+mips-*-elf* | mipsel-*-elf* | mipsr5900-*-elf* | mipsr5900el-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
tmake_file="mips/t-elf"
;;
+mips64r5900-*-elf* | mips64r5900el-*-elf*)
+ tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
+ tmake_file="mips/t-elf"
+ target_cpu_default="MASK_64BIT"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_N32"
+ ;;
mips64-*-elf* | mips64el-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
tmake_file="mips/t-elf"
@@ -2973,6 +2979,19 @@
;;
esac
;;
+ mips64r5900-*-*|mips64r5900el-*-*|mipsr5900-*-*|mipsr5900el-*-*)
+ with_arch=r5900
+ with_tune=r5900
+ if test x$with_llsc = x; then
+ # r5900 doesn't support ll, sc, lld and scd instructions:
+ with_llsc=no
+ fi
+ if test x$with_float = x; then
+ # r5900 doesn't support 64 bit float:
+ # 32 bit float doesn't comply with IEEE 754.
+ with_float=soft
+ fi
+ ;;
mips*-*-vxworks)
with_arch=mips2
;;
@@ -1029,6 +1029,19 @@
1, /* branch_cost */
4 /* memory_latency */
},
+ { /* R5900 */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (256), /* fp_mult_df */
+ COSTS_N_INSNS (8), /* fp_div_sf */
+ COSTS_N_INSNS (256), /* fp_div_df */
+ COSTS_N_INSNS (4), /* int_mult_si */
+ COSTS_N_INSNS (256), /* int_mult_di */
+ COSTS_N_INSNS (37), /* int_div_si */
+ COSTS_N_INSNS (256), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
{ /* R7000 */
/* The only costs that are changed here are
integer multiplication. */
@@ -13005,6 +13018,7 @@
case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
+ case PROCESSOR_R5900:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
@@ -16011,8 +16025,9 @@
cfun->machine->all_noreorder_p = false;
/* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
- because we rely on the assembler to work around some errata. */
- if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
+ because we rely on the assembler to work around some errata.
+ The r5900 has also several bugs. */
+ if (TARGET_FIX_VR4120 || TARGET_FIX_24K || TARGET_MIPS5900)
cfun->machine->all_noreorder_p = false;
/* The same is true for -mfix-vr4130 if we might generate MFLO or
@@ -222,6 +222,7 @@
#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
+#define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
@@ -252,6 +253,7 @@
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
+#define TUNE_MIPS5900 (mips_tune == PROCESSOR_R5900)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
@@ -833,10 +835,14 @@
/* ISA has the integer conditional move instructions introduced in mips4 and
ST Loongson 2E/2F. */
-#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
+#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
+ || TARGET_MIPS5900 \
+ || TARGET_LOONGSON_2EF)
/* ISA has LDC1 and SDC1. */
-#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
+ && !TARGET_MIPS16 \
+ && !TARGET_MIPS5900)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
@@ -946,6 +952,7 @@
/* ISA has data prefetch instructions. This controls use of 'pref'. */
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| TARGET_LOONGSON_2EF \
+ || TARGET_MIPS5900 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
@@ -1007,15 +1014,18 @@
and "addiu $4,$4,1". */
#define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
&& !TARGET_MIPS3900 \
+ && !TARGET_MIPS5900 \
&& !TARGET_MIPS16 \
&& !TARGET_MICROMIPS)
/* Likewise mtc1 and mfc1. */
#define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
+ && !TARGET_MIPS5900 \
&& !TARGET_LOONGSON_2EF)
/* Likewise floating-point comparisons. */
#define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
+ && !TARGET_MIPS5900 \
&& !TARGET_LOONGSON_2EF)
/* True if mflo and mfhi can be immediately followed by instructions
@@ -1035,6 +1045,7 @@
|| ISA_MIPS64 \
|| ISA_MIPS64R2 \
|| TARGET_MIPS5500 \
+ || TARGET_MIPS5900 \
|| TARGET_LOONGSON_2EF)
/* ISA includes synci, jr.hb and jalr.hb. */
@@ -68,6 +68,7 @@
MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
MIPS_CPU ("r4700", PROCESSOR_R4700, 3, 0)
+MIPS_CPU ("r5900", PROCESSOR_R5900, 3, 0)
/* ST Loongson 2E/2F processors. */
MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY)
@@ -55,6 +55,7 @@
r5000
r5400
r5500
+ r5900
r7000
r8000
r9000
@@ -755,7 +756,9 @@
;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
- (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
+ (CC "TARGET_HARD_FLOAT
+ && !TARGET_LOONGSON_2EF
+ && !TARGET_MIPS5900")])
;; 32-bit integer moves for which we provide move patterns.
(define_mode_iterator IMOVE32
@@ -284,6 +284,8 @@
| mips64vr4300 | mips64vr4300el \
| mips64vr5000 | mips64vr5000el \
| mips64vr5900 | mips64vr5900el \
+ | mips64r5900 | mips64r5900el \
+ | mipsr5900 | mipsr5900el \
| mipsisa32 | mipsisa32el \
| mipsisa32r2 | mipsisa32r2el \
| mipsisa64 | mipsisa64el \
@@ -402,6 +404,8 @@
| mips64vr4300-* | mips64vr4300el-* \
| mips64vr5000-* | mips64vr5000el-* \
| mips64vr5900-* | mips64vr5900el-* \
+ | mips64r5900-* | mips64r5900el-* \
+ | mipsr5900-* | mipsr5900el-* \
| mipsisa32-* | mipsisa32el-* \
| mipsisa32r2-* | mipsisa32r2el-* \
| mipsisa64-* | mipsisa64el-* \