| Message ID | 1369046369-12489-4-git-send-email-josephl@nvidia.com |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Monday 20 May 2013, Joseph Lo wrote: > + cpu_to_csr_req r1, r0 > + mov32 r2, TEGRA_FLOW_CTRL_BASE > + ldr r1, [r2, r1] This causes build errors now, since cpu_to_csr_req is not defined anywhere. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 05/31/2013 04:41 PM, Arnd Bergmann wrote: > On Monday 20 May 2013, Joseph Lo wrote: >> + cpu_to_csr_req r1, r0 >> + mov32 r2, TEGRA_FLOW_CTRL_BASE >> + ldr r1, [r2, r1] > > This causes build errors now, since cpu_to_csr_req is not defined anywhere. What build error are you seeing? I built next-20130531 earlier today without any issue. I do remember making a similar comment during review of this patch that cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to another patch in the series which had added it, or something like that. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Saturday 01 June 2013, Stephen Warren wrote: > On 05/31/2013 04:41 PM, Arnd Bergmann wrote: > > On Monday 20 May 2013, Joseph Lo wrote: > >> + cpu_to_csr_req r1, r0 > >> + mov32 r2, TEGRA_FLOW_CTRL_BASE > >> + ldr r1, [r2, r1] > > > > This causes build errors now, since cpu_to_csr_req is not defined anywhere. > > What build error are you seeing? I built next-20130531 earlier today > without any issue. > > I do remember making a similar comment during review of this patch that > cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to > another patch in the series which had added it, or something like that. Sorry, I should have mentioned it was using randconfig, all the defconfig builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC", but Tegra2 is normally enabled in defconfig, so it does not get built. I suspect the #ifdef is wrong as well, and should have been "if tegra3 or tegra4" instead. Joseph, can you clarify the intent of this? Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sat, 2013-06-01 at 17:47 +0800, Arnd Bergmann wrote: > On Saturday 01 June 2013, Stephen Warren wrote: > > On 05/31/2013 04:41 PM, Arnd Bergmann wrote: > > > On Monday 20 May 2013, Joseph Lo wrote: > > >> + cpu_to_csr_req r1, r0 > > >> + mov32 r2, TEGRA_FLOW_CTRL_BASE > > >> + ldr r1, [r2, r1] > > > > > > This causes build errors now, since cpu_to_csr_req is not defined anywhere. > > > > What build error are you seeing? I built next-20130531 earlier today > > without any issue. > > > > I do remember making a similar comment during review of this patch that > > cpu_to_csr_req wasn't defined anywhere, but IIRC Joseph pointed me to > > another patch in the series which had added it, or something like that. > > Sorry, I should have mentioned it was using randconfig, all the defconfig > builds work fine. The code is inside of "#ifndef CONFIG_ARCH_TEGRA_2x_SOC", > but Tegra2 is normally enabled in defconfig, so it does not get built. > > I suspect the #ifdef is wrong as well, and should have been "if tegra3 > or tegra4" instead. Joseph, can you clarify the intent of this? > > Arnd Arnd, I think the "ifdef" should be removed here because we had a runtime Tegra SoC detection code here, the "ifdef" here would cause the code won't be built for the tegra_defconfig that we are using. And a typo need to fix here, it should be "cpu_to_csr_reg" not "cpu_to_csr_req". Sorry. Thanks for report. Will provide a fix. Joseph -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 40af405..424e01f 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -47,23 +47,27 @@ ENTRY(tegra_resume) THUMB( it ne ) bne cpu_resume @ no -#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifndef CONFIG_ARCH_TEGRA_2x_SOC /* Are we on Tegra20? */ tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 cmp r6, #TEGRA20 beq 1f @ Yes /* Clear the flow controller flags for this CPU. */ - mov32 r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR @ CPU0 CSR - ldr r1, [r2] + cpu_to_csr_req r1, r0 + mov32 r2, TEGRA_FLOW_CTRL_BASE + ldr r1, [r2, r1] /* Clear event & intr flag */ orr r1, r1, \ #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG - movw r0, #0x0FFD @ enable, cluster_switch, immed, & bitmaps + movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps + @ & ext flags for CPU power mgnt bic r1, r1, r0 str r1, [r2] 1: #endif + check_cpu_part_num 0xc09, r8, r9 + bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE @@ -74,6 +78,7 @@ ENTRY(tegra_resume) /* L2 cache resume & re-enable */ l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr +not_ca9: b cpu_resume ENDPROC(tegra_resume)
Tegra114 had a newer flow controller hardware that makes its behavior and configurations are different with other Tegra series. We fix the common resume function of tegra_resume to make it can work on Tegra114 by checking SoC ID. And also checking CPU primary part number to isolate the support code for Cortex A9 and A15. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- V2: * update the commit message * update the comment message for the CSR flags --- arch/arm/mach-tegra/reset-handler.S | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)