| Message ID | 1368241015-14362-1-git-send-email-amartin@nvidia.com |
|---|---|
| State | Accepted |
| Delegated to: | Tom Warren |
| Headers | show |
On Fri, May 10, 2013 at 8:56 PM, Allen Martin <amartin@nvidia.com> wrote: > When adjusting peripheral clocks always use find_best_divider() > instead of clk_get_divider() even when a secondary divider is not > available. In the case where is requested clock is too slow to be > derived from the parent clock this allows a best effort to get close > to the requested clock. > > This comes up for commands like "sf" where the user can pass a clock > speed on the command line or "sspi" where the clock is hardcoded to > 1MHz, but the Tegra114 SPI controller can't go that low. > > Signed-off-by: Allen Martin <amartin@nvidia.com> Seems right to me, Acked-by: Simon Glass <sjg@chromium.org>
On Mon, May 13, 2013 at 10:24:17AM -0700, Tom Warren wrote: > Allen, > > > -----Original Message----- > > From: sjg@google.com [mailto:sjg@google.com] On Behalf Of Simon Glass > > Sent: Friday, May 10, 2013 8:06 PM > > To: Allen Martin > > Cc: Tom Warren; Stephen Warren; U-Boot Mailing List > > Subject: Re: [PATCH] Tegra: clk: always use find_best_divider() for periph > > clocks > > > > On Fri, May 10, 2013 at 8:56 PM, Allen Martin <amartin@nvidia.com> wrote: > > > When adjusting peripheral clocks always use find_best_divider() > > > instead of clk_get_divider() even when a secondary divider is not > > > available. In the case where is requested clock is too slow to be > > > derived from the parent clock this allows a best effort to get close > > > to the requested clock. > > > > > > This comes up for commands like "sf" where the user can pass a clock > > > speed on the command line or "sspi" where the clock is hardcoded to > > > 1MHz, but the Tegra114 SPI controller can't go that low. > > Did you test all other periphs and check their config'd clocks to make sure this doesn't affect anything else negatively? This proc is pretty universal (called by clock_start_periph_pll, which is used by MMC/I2C/USB/display drivers). > I tested a handful of peripherals on dalmore, but you're right this is generic enough that it warrants a more thorough test scrubbing. I'll try to hit all the peripherals I can across all chipsets and report back. -Allen
On Mon, May 13, 2013 at 10:24:17AM -0700, Tom Warren wrote: > Allen, > > > -----Original Message----- > > From: sjg@google.com [mailto:sjg@google.com] On Behalf Of Simon Glass > > Sent: Friday, May 10, 2013 8:06 PM > > To: Allen Martin > > Cc: Tom Warren; Stephen Warren; U-Boot Mailing List > > Subject: Re: [PATCH] Tegra: clk: always use find_best_divider() for periph > > clocks > > > > On Fri, May 10, 2013 at 8:56 PM, Allen Martin <amartin@nvidia.com> wrote: > > > When adjusting peripheral clocks always use find_best_divider() > > > instead of clk_get_divider() even when a secondary divider is not > > > available. In the case where is requested clock is too slow to be > > > derived from the parent clock this allows a best effort to get close > > > to the requested clock. > > > > > > This comes up for commands like "sf" where the user can pass a clock > > > speed on the command line or "sspi" where the clock is hardcoded to > > > 1MHz, but the Tegra114 SPI controller can't go that low. > > Did you test all other periphs and check their config'd clocks to make sure this doesn't affect anything else negatively? This proc is pretty universal (called by clock_start_periph_pll, which is used by MMC/I2C/USB/display drivers). > Testing done: tegra20 seaboard: usb read/write i2c read emmc read sdcard read/write lcd uart read/write tegra20 trimslice: spi read uart read/write tegra30 cardhu: spi read/write uart read/write i2c read sdcard read/write emmc read tegra114 dalmore: iwc read sdcard read/write emmc read uart read/write -Allen
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 9156d00..268fb91 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, unsigned effective_rate; int mux_bits, divider_bits, source; int divider; + int xdiv = 0; /* work out the source clock and set it */ source = get_periph_clock_source(periph_id, parent, &mux_bits, ÷r_bits); + divider = find_best_divider(divider_bits, pll_rate[parent], + rate, &xdiv); if (extra_div) - divider = find_best_divider(divider_bits, pll_rate[parent], - rate, extra_div); - else - divider = clk_get_divider(divider_bits, pll_rate[parent], - rate); + *extra_div = xdiv; + assert(divider >= 0); if (adjust_periph_pll(periph_id, source, mux_bits, divider)) return -1U;
When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin <amartin@nvidia.com> --- arch/arm/cpu/tegra-common/clock.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)