| Message ID | 1367525344-7755-5-git-send-email-hpoussin@reactos.org |
|---|---|
| State | New |
| Headers | show |
On Thu, May 2, 2013 at 10:09 PM, Hervé Poussineau <hpoussin@reactos.org> wrote: > As m48t59 devices can only be created with m48t59_init() or m48t59_init_isa(), > we know exactly which nvram types are required. Register only those three > types. Wasn't this patch NACKed by Blue? > Remove .model and .size properties as they can be infered from nvram name. > > Rename type to 'isa-*' (and 'sysbus-*') to do like other devices ISA devices > (isa-ide, isa-parallel, isa-serial...) > > Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> > --- > hw/timer/m48t59.c | 248 +++++++++++++++++++++++++++++++++++++---------------- > 1 file changed, 172 insertions(+), 76 deletions(-) > > diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c > index fb78d20..23a6ab3 100644 > --- a/hw/timer/m48t59.c > +++ b/hw/timer/m48t59.c > @@ -2,6 +2,7 @@ > * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms > * > * Copyright (c) 2003-2005, 2007 Jocelyn Mayer > + * Copyright (c) 2013 Hervé Poussineau > * > * Permission is hereby granted, free of charge, to any person obtaining a copy > * of this software and associated documentation files (the "Software"), to deal > @@ -37,12 +38,31 @@ > #define NVRAM_PRINTF(fmt, ...) do { } while (0) > #endif > > +#define TYPE_M48TXX_SYS_BUS "m48txx-sysbus" > +#define M48TXX_SYS_BUS_CLASS(klass) \ > + OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS) > +#define M48TXX_SYS_BUS(obj) \ > + OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS) > + > +#define TYPE_M48TXX_ISA "m48txx-isa" > +#define M48TXX_ISA_CLASS(klass) \ > + OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) > +#define M48TXX_ISA(obj) \ > + OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) > + > /* > * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has > * alarm and a watchdog timer and related control registers. In the > * PPC platform there is also a nvram lock function. > */ > > +typedef struct M48txxInfo { > + const char *isa_name; > + const char *sysbus_name; > + uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ > + uint32_t size; > +} M48txxInfo; > + > /* > * Chipset docs: > * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf > @@ -54,7 +74,6 @@ struct M48t59State { > /* Hardware parameters */ > qemu_irq IRQ; > MemoryRegion iomem; > - uint32_t io_base; > uint32_t size; > /* RTC management */ > time_t time_offset; > @@ -72,22 +91,45 @@ struct M48t59State { > uint8_t lock; > }; > > -#define TYPE_ISA_M48T59 "m48t59_isa" > -#define ISA_M48T59(obj) \ > - OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) > - > -typedef struct M48t59ISAState { > +typedef struct M48txxISAState { > ISADevice parent_obj; > - > M48t59State state; > + uint32_t io_base; > MemoryRegion io; > -} M48t59ISAState; > +} M48txxISAState; > + > +typedef struct M48txxISADeviceClass { > + ISADeviceClass parent_class; > + M48txxInfo info; > +} M48txxISADeviceClass; > > -typedef struct M48t59SysBusState { > - SysBusDevice busdev; > +typedef struct M48txxSysBusState { > + SysBusDevice parent_obj; > M48t59State state; > MemoryRegion io; > -} M48t59SysBusState; > +} M48txxSysBusState; > + > +typedef struct M48txxSysBusDeviceClass { > + SysBusDeviceClass parent_class; > + M48txxInfo info; > +} M48txxSysBusDeviceClass; > + > +static M48txxInfo m48txx_info[] = { > + { > + .sysbus_name = "sysbus-m48t02", > + .model = 2, > + .size = 0x800, > + },{ > + .sysbus_name = "sysbus-m48t08", > + .model = 8, > + .size = 0x2000, > + },{ > + .isa_name = "isa-m48t59", > + .model = 59, > + .size = 0x2000, > + } > +}; > + > > /* Fake timer functions */ > > @@ -613,7 +655,7 @@ static void m48t59_reset_common(M48t59State *NVRAM) > > static void m48t59_reset_isa(DeviceState *d) > { > - M48t59ISAState *isa = ISA_M48T59(d); > + M48txxISAState *isa = M48TXX_ISA(d); > M48t59State *NVRAM = &isa->state; > > m48t59_reset_common(NVRAM); > @@ -621,7 +663,7 @@ static void m48t59_reset_isa(DeviceState *d) > > static void m48t59_reset_sysbus(DeviceState *d) > { > - M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); > + M48txxSysBusState *sys = M48TXX_SYS_BUS(d); > M48t59State *NVRAM = &sys->state; > > m48t59_reset_common(NVRAM); > @@ -643,47 +685,62 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, > { > DeviceState *dev; > SysBusDevice *s; > - M48t59SysBusState *d; > + M48txxSysBusState *d; > M48t59State *state; > + int i; > > - dev = qdev_create(NULL, "m48t59"); > - qdev_prop_set_uint32(dev, "model", model); > - qdev_prop_set_uint32(dev, "size", size); > - qdev_prop_set_uint32(dev, "io_base", io_base); > - qdev_init_nofail(dev); > - s = SYS_BUS_DEVICE(dev); > - d = FROM_SYSBUS(M48t59SysBusState, s); > - state = &d->state; > - sysbus_connect_irq(s, 0, IRQ); > - if (io_base != 0) { > - memory_region_add_subregion(get_system_io(), io_base, > - sysbus_mmio_get_region(dev, 1)); > - } > - if (mem_base != 0) { > - sysbus_mmio_map(s, 0, mem_base); > + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (!m48txx_info[i].sysbus_name || > + m48txx_info[i].size != size || > + m48txx_info[i].model != model) { > + continue; > + } > + > + dev = qdev_create(NULL, m48txx_info[i].sysbus_name); > + qdev_init_nofail(dev); > + s = SYS_BUS_DEVICE(dev); > + d = M48TXX_SYS_BUS(s); > + state = &d->state; > + sysbus_connect_irq(s, 0, IRQ); > + memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); > + if (io_base != 0) { > + memory_region_add_subregion(get_system_io(), io_base, > + sysbus_mmio_get_region(s, 1)); > + } > + if (mem_base != 0) { > + sysbus_mmio_map(s, 0, mem_base); > + } > + > + return state; > } > > - return state; > + assert(false); > + return NULL; > } > > M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, > int model) > { > - M48t59ISAState *d; > - ISADevice *isadev; > + M48txxISAState *d; > DeviceState *dev; > - M48t59State *s; > - > - isadev = isa_create(bus, TYPE_ISA_M48T59); > - dev = DEVICE(isadev); > - qdev_prop_set_uint32(dev, "model", model); > - qdev_prop_set_uint32(dev, "size", size); > - qdev_prop_set_uint32(dev, "io_base", io_base); > - qdev_init_nofail(dev); > - d = ISA_M48T59(isadev); > - s = &d->state; > - > - return s; > + int i; > + > + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (!m48txx_info[i].isa_name || > + m48txx_info[i].size != size || > + m48txx_info[i].model != model) { > + continue; > + } > + > + dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name)); > + qdev_prop_set_uint32(dev, "iobase", io_base); > + qdev_init_nofail(dev); > + d = container_of(ISA_DEVICE(dev), M48txxISAState, parent_obj); > + return &d->state; > + } > + > + assert(false); > + return NULL; > } > > static void m48t59_init_common(M48t59State *s) > @@ -700,14 +757,19 @@ static void m48t59_init_common(M48t59State *s) > > static int m48t59_init_isa1(ISADevice *dev) > { > - M48t59ISAState *d = ISA_M48T59(dev); > + ISADeviceClass *ic = ISA_DEVICE_GET_CLASS(dev); > + M48txxISADeviceClass *u = container_of(ic, M48txxISADeviceClass, > + parent_class); > + M48txxISAState *d = container_of(dev, M48txxISAState, parent_obj); > M48t59State *s = &d->state; > > + s->model = u->info.model; > + s->size = u->info.size; > isa_init_irq(dev, &s->IRQ, 8); > m48t59_init_common(s); > memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); > - if (s->io_base != 0) { > - isa_register_ioport(dev, &d->io, s->io_base); > + if (d->io_base != 0) { > + isa_register_ioport(dev, &d->io, d->io_base); > } > > return 0; > @@ -715,9 +777,14 @@ static int m48t59_init_isa1(ISADevice *dev) > > static int m48t59_init1(SysBusDevice *dev) > { > - M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); > + SysBusDeviceClass *k = SYS_BUS_DEVICE_GET_CLASS(dev); > + M48txxSysBusDeviceClass *u = container_of(k, M48txxSysBusDeviceClass, > + parent_class); > + M48txxSysBusState *d = container_of(dev, M48txxSysBusState, parent_obj); > M48t59State *s = &d->state; > > + s->model = u->info.model; > + s->size = u->info.size; > sysbus_init_irq(dev, &s->IRQ); > > memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size); > @@ -730,57 +797,86 @@ static int m48t59_init1(SysBusDevice *dev) > } > > static Property m48t59_isa_properties[] = { > - DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), > - DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), > - DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), > + DEFINE_PROP_HEX32("iobase", M48txxISAState, io_base, 0x74), > DEFINE_PROP_END_OF_LIST(), > }; > > -static void m48t59_isa_class_init(ObjectClass *klass, void *data) > +static void m48txx_isa_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); > + M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); > + M48txxInfo *info = data; > + > ic->init = m48t59_init_isa1; > dc->no_user = 1; > dc->reset = m48t59_reset_isa; > - dc->props = m48t59_isa_properties; > + if (info) { > + dc->props = m48t59_isa_properties; > + u->info = *info; > + } > } > > -static const TypeInfo m48t59_isa_info = { > - .name = TYPE_ISA_M48T59, > - .parent = TYPE_ISA_DEVICE, > - .instance_size = sizeof(M48t59ISAState), > - .class_init = m48t59_isa_class_init, > -}; > - > -static Property m48t59_properties[] = { > - DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), > - DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), > - DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), > - DEFINE_PROP_END_OF_LIST(), > -}; > - > -static void m48t59_class_init(ObjectClass *klass, void *data) > +static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); > + M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass); > + M48txxInfo *info = data; > > k->init = m48t59_init1; > dc->reset = m48t59_reset_sysbus; > - dc->props = m48t59_properties; > + if (info) { > + u->info = *info; > + } > } > > -static const TypeInfo m48t59_info = { > - .name = "m48t59", > - .parent = TYPE_SYS_BUS_DEVICE, > - .instance_size = sizeof(M48t59SysBusState), > - .class_init = m48t59_class_init, > +static const TypeInfo m48txx_sysbus_type_info = { > + .name = TYPE_M48TXX_SYS_BUS, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(M48txxSysBusState), > + .abstract = true, > + .class_init = m48txx_sysbus_class_init, > +}; > + > +static const TypeInfo m48txx_isa_type_info = { > + .name = TYPE_M48TXX_ISA, > + .parent = TYPE_ISA_DEVICE, > + .instance_size = sizeof(M48txxISAState), > + .abstract = true, > + .class_init = m48txx_isa_class_init, > }; > > static void m48t59_register_types(void) > { > - type_register_static(&m48t59_info); > - type_register_static(&m48t59_isa_info); > + TypeInfo sysbus_type_info = { > + .parent = TYPE_M48TXX_SYS_BUS, > + .class_size = sizeof(M48txxSysBusDeviceClass), > + .class_init = m48txx_sysbus_class_init, > + }; > + TypeInfo isa_type_info = { > + .parent = TYPE_M48TXX_ISA, > + .class_size = sizeof(M48txxISADeviceClass), > + .class_init = m48txx_isa_class_init, > + }; > + int i; > + > + type_register_static(&m48txx_sysbus_type_info); > + type_register_static(&m48txx_isa_type_info); > + > + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { > + if (m48txx_info[i].sysbus_name) { > + sysbus_type_info.name = m48txx_info[i].sysbus_name; > + sysbus_type_info.class_data = &m48txx_info[i]; > + type_register(&sysbus_type_info); > + } > + > + if (m48txx_info[i].isa_name) { > + isa_type_info.name = m48txx_info[i].isa_name; > + isa_type_info.class_data = &m48txx_info[i]; > + type_register(&isa_type_info); > + } > + } > } > > type_init(m48t59_register_types) > -- > 1.7.10.4 > > -- Regards, Artyom Tarasenko linux/sparc and solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu
Artyom Tarasenko a écrit : > On Thu, May 2, 2013 at 10:09 PM, Hervé Poussineau <hpoussin@reactos.org> wrote: >> As m48t59 devices can only be created with m48t59_init() or m48t59_init_isa(), >> we know exactly which nvram types are required. Register only those three >> types. > > Wasn't this patch NACKed by Blue? I think I changed what's requested, ie I kept the io-base property of the ISA variant, so the sun4u emulation can be changed later to the right address. However, fixing sun4u emulation is not part of this patchset. Otherwise, if I didn't understood, please elaborate. Regards, Hervé
On Fri, May 3, 2013 at 7:50 AM, Hervé Poussineau <hpoussin@reactos.org> wrote: > Artyom Tarasenko a écrit : > >> On Thu, May 2, 2013 at 10:09 PM, Hervé Poussineau <hpoussin@reactos.org> >> wrote: >>> >>> As m48t59 devices can only be created with m48t59_init() or >>> m48t59_init_isa(), >>> we know exactly which nvram types are required. Register only those three >>> types. >> >> >> Wasn't this patch NACKed by Blue? > > > I think I changed what's requested, ie I kept the io-base property of the > ISA variant, so the sun4u emulation can be changed later to the right > address. However, fixing sun4u emulation is not part of this patchset. Sorry, I misread the patch. The value 0x74 is now just a default value for the isa port, right? How would I create an isa m48t59 card on some other port? Artyom -- Regards, Artyom Tarasenko linux/sparc and solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu
Artyom Tarasenko a écrit : > On Fri, May 3, 2013 at 7:50 AM, Hervé Poussineau <hpoussin@reactos.org> wrote: >> Artyom Tarasenko a écrit : >> >>> On Thu, May 2, 2013 at 10:09 PM, Hervé Poussineau <hpoussin@reactos.org> >>> wrote: >>>> As m48t59 devices can only be created with m48t59_init() or >>>> m48t59_init_isa(), >>>> we know exactly which nvram types are required. Register only those three >>>> types. >>> >>> Wasn't this patch NACKed by Blue? >> >> I think I changed what's requested, ie I kept the io-base property of the >> ISA variant, so the sun4u emulation can be changed later to the right >> address. However, fixing sun4u emulation is not part of this patchset. > > Sorry, I misread the patch. The value 0x74 is now just a default value for > the isa port, right? How would I create an isa m48t59 card on some other port? Yes, 0x74 is now the default value. You can create an isa m48t59 device on port 0x100 - with command line: -device isa-m4859,iobase=0x100 - in code using the helper: m48t59_init_isa(isa_bus, 0x100, 0x2000, 59); - with QOM: DeviceState *dev; dev = DEVICE(isa_create(isa_bus, "isa-m48t59")); qdev_prop_set_uint16(dev, "iobase", 0x100); qdev_init_nofail(dev); Hervé
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index fb78d20..23a6ab3 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -2,6 +2,7 @@ * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms * * Copyright (c) 2003-2005, 2007 Jocelyn Mayer + * Copyright (c) 2013 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -37,12 +38,31 @@ #define NVRAM_PRINTF(fmt, ...) do { } while (0) #endif +#define TYPE_M48TXX_SYS_BUS "m48txx-sysbus" +#define M48TXX_SYS_BUS_CLASS(klass) \ + OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS) +#define M48TXX_SYS_BUS(obj) \ + OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS) + +#define TYPE_M48TXX_ISA "m48txx-isa" +#define M48TXX_ISA_CLASS(klass) \ + OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) +#define M48TXX_ISA(obj) \ + OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) + /* * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has * alarm and a watchdog timer and related control registers. In the * PPC platform there is also a nvram lock function. */ +typedef struct M48txxInfo { + const char *isa_name; + const char *sysbus_name; + uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ + uint32_t size; +} M48txxInfo; + /* * Chipset docs: * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf @@ -54,7 +74,6 @@ struct M48t59State { /* Hardware parameters */ qemu_irq IRQ; MemoryRegion iomem; - uint32_t io_base; uint32_t size; /* RTC management */ time_t time_offset; @@ -72,22 +91,45 @@ struct M48t59State { uint8_t lock; }; -#define TYPE_ISA_M48T59 "m48t59_isa" -#define ISA_M48T59(obj) \ - OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) - -typedef struct M48t59ISAState { +typedef struct M48txxISAState { ISADevice parent_obj; - M48t59State state; + uint32_t io_base; MemoryRegion io; -} M48t59ISAState; +} M48txxISAState; + +typedef struct M48txxISADeviceClass { + ISADeviceClass parent_class; + M48txxInfo info; +} M48txxISADeviceClass; -typedef struct M48t59SysBusState { - SysBusDevice busdev; +typedef struct M48txxSysBusState { + SysBusDevice parent_obj; M48t59State state; MemoryRegion io; -} M48t59SysBusState; +} M48txxSysBusState; + +typedef struct M48txxSysBusDeviceClass { + SysBusDeviceClass parent_class; + M48txxInfo info; +} M48txxSysBusDeviceClass; + +static M48txxInfo m48txx_info[] = { + { + .sysbus_name = "sysbus-m48t02", + .model = 2, + .size = 0x800, + },{ + .sysbus_name = "sysbus-m48t08", + .model = 8, + .size = 0x2000, + },{ + .isa_name = "isa-m48t59", + .model = 59, + .size = 0x2000, + } +}; + /* Fake timer functions */ @@ -613,7 +655,7 @@ static void m48t59_reset_common(M48t59State *NVRAM) static void m48t59_reset_isa(DeviceState *d) { - M48t59ISAState *isa = ISA_M48T59(d); + M48txxISAState *isa = M48TXX_ISA(d); M48t59State *NVRAM = &isa->state; m48t59_reset_common(NVRAM); @@ -621,7 +663,7 @@ static void m48t59_reset_isa(DeviceState *d) static void m48t59_reset_sysbus(DeviceState *d) { - M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); + M48txxSysBusState *sys = M48TXX_SYS_BUS(d); M48t59State *NVRAM = &sys->state; m48t59_reset_common(NVRAM); @@ -643,47 +685,62 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, { DeviceState *dev; SysBusDevice *s; - M48t59SysBusState *d; + M48txxSysBusState *d; M48t59State *state; + int i; - dev = qdev_create(NULL, "m48t59"); - qdev_prop_set_uint32(dev, "model", model); - qdev_prop_set_uint32(dev, "size", size); - qdev_prop_set_uint32(dev, "io_base", io_base); - qdev_init_nofail(dev); - s = SYS_BUS_DEVICE(dev); - d = FROM_SYSBUS(M48t59SysBusState, s); - state = &d->state; - sysbus_connect_irq(s, 0, IRQ); - if (io_base != 0) { - memory_region_add_subregion(get_system_io(), io_base, - sysbus_mmio_get_region(dev, 1)); - } - if (mem_base != 0) { - sysbus_mmio_map(s, 0, mem_base); + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (!m48txx_info[i].sysbus_name || + m48txx_info[i].size != size || + m48txx_info[i].model != model) { + continue; + } + + dev = qdev_create(NULL, m48txx_info[i].sysbus_name); + qdev_init_nofail(dev); + s = SYS_BUS_DEVICE(dev); + d = M48TXX_SYS_BUS(s); + state = &d->state; + sysbus_connect_irq(s, 0, IRQ); + memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); + if (io_base != 0) { + memory_region_add_subregion(get_system_io(), io_base, + sysbus_mmio_get_region(s, 1)); + } + if (mem_base != 0) { + sysbus_mmio_map(s, 0, mem_base); + } + + return state; } - return state; + assert(false); + return NULL; } M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, int model) { - M48t59ISAState *d; - ISADevice *isadev; + M48txxISAState *d; DeviceState *dev; - M48t59State *s; - - isadev = isa_create(bus, TYPE_ISA_M48T59); - dev = DEVICE(isadev); - qdev_prop_set_uint32(dev, "model", model); - qdev_prop_set_uint32(dev, "size", size); - qdev_prop_set_uint32(dev, "io_base", io_base); - qdev_init_nofail(dev); - d = ISA_M48T59(isadev); - s = &d->state; - - return s; + int i; + + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (!m48txx_info[i].isa_name || + m48txx_info[i].size != size || + m48txx_info[i].model != model) { + continue; + } + + dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name)); + qdev_prop_set_uint32(dev, "iobase", io_base); + qdev_init_nofail(dev); + d = container_of(ISA_DEVICE(dev), M48txxISAState, parent_obj); + return &d->state; + } + + assert(false); + return NULL; } static void m48t59_init_common(M48t59State *s) @@ -700,14 +757,19 @@ static void m48t59_init_common(M48t59State *s) static int m48t59_init_isa1(ISADevice *dev) { - M48t59ISAState *d = ISA_M48T59(dev); + ISADeviceClass *ic = ISA_DEVICE_GET_CLASS(dev); + M48txxISADeviceClass *u = container_of(ic, M48txxISADeviceClass, + parent_class); + M48txxISAState *d = container_of(dev, M48txxISAState, parent_obj); M48t59State *s = &d->state; + s->model = u->info.model; + s->size = u->info.size; isa_init_irq(dev, &s->IRQ, 8); m48t59_init_common(s); memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); - if (s->io_base != 0) { - isa_register_ioport(dev, &d->io, s->io_base); + if (d->io_base != 0) { + isa_register_ioport(dev, &d->io, d->io_base); } return 0; @@ -715,9 +777,14 @@ static int m48t59_init_isa1(ISADevice *dev) static int m48t59_init1(SysBusDevice *dev) { - M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); + SysBusDeviceClass *k = SYS_BUS_DEVICE_GET_CLASS(dev); + M48txxSysBusDeviceClass *u = container_of(k, M48txxSysBusDeviceClass, + parent_class); + M48txxSysBusState *d = container_of(dev, M48txxSysBusState, parent_obj); M48t59State *s = &d->state; + s->model = u->info.model; + s->size = u->info.size; sysbus_init_irq(dev, &s->IRQ); memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size); @@ -730,57 +797,86 @@ static int m48t59_init1(SysBusDevice *dev) } static Property m48t59_isa_properties[] = { - DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), - DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), - DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), + DEFINE_PROP_HEX32("iobase", M48txxISAState, io_base, 0x74), DEFINE_PROP_END_OF_LIST(), }; -static void m48t59_isa_class_init(ObjectClass *klass, void *data) +static void m48txx_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); + M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); + M48txxInfo *info = data; + ic->init = m48t59_init_isa1; dc->no_user = 1; dc->reset = m48t59_reset_isa; - dc->props = m48t59_isa_properties; + if (info) { + dc->props = m48t59_isa_properties; + u->info = *info; + } } -static const TypeInfo m48t59_isa_info = { - .name = TYPE_ISA_M48T59, - .parent = TYPE_ISA_DEVICE, - .instance_size = sizeof(M48t59ISAState), - .class_init = m48t59_isa_class_init, -}; - -static Property m48t59_properties[] = { - DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), - DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), - DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), - DEFINE_PROP_END_OF_LIST(), -}; - -static void m48t59_class_init(ObjectClass *klass, void *data) +static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass); + M48txxInfo *info = data; k->init = m48t59_init1; dc->reset = m48t59_reset_sysbus; - dc->props = m48t59_properties; + if (info) { + u->info = *info; + } } -static const TypeInfo m48t59_info = { - .name = "m48t59", - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(M48t59SysBusState), - .class_init = m48t59_class_init, +static const TypeInfo m48txx_sysbus_type_info = { + .name = TYPE_M48TXX_SYS_BUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(M48txxSysBusState), + .abstract = true, + .class_init = m48txx_sysbus_class_init, +}; + +static const TypeInfo m48txx_isa_type_info = { + .name = TYPE_M48TXX_ISA, + .parent = TYPE_ISA_DEVICE, + .instance_size = sizeof(M48txxISAState), + .abstract = true, + .class_init = m48txx_isa_class_init, }; static void m48t59_register_types(void) { - type_register_static(&m48t59_info); - type_register_static(&m48t59_isa_info); + TypeInfo sysbus_type_info = { + .parent = TYPE_M48TXX_SYS_BUS, + .class_size = sizeof(M48txxSysBusDeviceClass), + .class_init = m48txx_sysbus_class_init, + }; + TypeInfo isa_type_info = { + .parent = TYPE_M48TXX_ISA, + .class_size = sizeof(M48txxISADeviceClass), + .class_init = m48txx_isa_class_init, + }; + int i; + + type_register_static(&m48txx_sysbus_type_info); + type_register_static(&m48txx_isa_type_info); + + for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) { + if (m48txx_info[i].sysbus_name) { + sysbus_type_info.name = m48txx_info[i].sysbus_name; + sysbus_type_info.class_data = &m48txx_info[i]; + type_register(&sysbus_type_info); + } + + if (m48txx_info[i].isa_name) { + isa_type_info.name = m48txx_info[i].isa_name; + isa_type_info.class_data = &m48txx_info[i]; + type_register(&isa_type_info); + } + } } type_init(m48t59_register_types)
As m48t59 devices can only be created with m48t59_init() or m48t59_init_isa(), we know exactly which nvram types are required. Register only those three types. Remove .model and .size properties as they can be infered from nvram name. Rename type to 'isa-*' (and 'sysbus-*') to do like other devices ISA devices (isa-ide, isa-parallel, isa-serial...) Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> --- hw/timer/m48t59.c | 248 +++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 172 insertions(+), 76 deletions(-)