Message ID | 1367178711-8232-9-git-send-email-aneesh.kumar@linux.vnet.ibm.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
On Mon, Apr 29, 2013 at 01:21:49AM +0530, Aneesh Kumar K.V wrote: > From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> > > We enable only if the we support 16MB page size. > > Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/pgtable-ppc64.h | 3 +-- > arch/powerpc/mm/pgtable_64.c | 28 ++++++++++++++++++++++++++++ > 2 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h > index 97fc839..d65534b 100644 > --- a/arch/powerpc/include/asm/pgtable-ppc64.h > +++ b/arch/powerpc/include/asm/pgtable-ppc64.h > @@ -426,8 +426,7 @@ static inline unsigned long pmd_pfn(pmd_t pmd) > return pmd_val(pmd) >> PTE_RPN_SHIFT; > } > > -/* We will enable it in the last patch */ > -#define has_transparent_hugepage() 0 > +extern int has_transparent_hugepage(void); > #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ > > static inline int pmd_young(pmd_t pmd) > diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c > index 54216c1..b742d6f 100644 > --- a/arch/powerpc/mm/pgtable_64.c > +++ b/arch/powerpc/mm/pgtable_64.c > @@ -754,6 +754,34 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, > return; > } > > +int has_transparent_hugepage(void) > +{ > + if (!mmu_has_feature(MMU_FTR_16M_PAGE)) > + return 0; > + /* > + * We support THP only if HPAGE_SHIFT is 16MB. > + */ > + if (!HPAGE_SHIFT || (HPAGE_SHIFT != mmu_psize_defs[MMU_PAGE_16M].shift)) > + return 0; Again, THP should not be dependent on the value of HPAGE_SHIFT. Just checking that mmu_psize_defsz[MMU_PAGE_16M].shift == 24 should be sufficient (i.e. that 16M hugepages are supported). > + /* > + * We need to make sure that we support 16MB hugepage in a segement > + * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE > + * of 64K. > + */ > + /* > + * If we have 64K HPTE, we will be using that by default > + */ > + if (mmu_psize_defs[MMU_PAGE_64K].shift && > + (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1)) > + return 0; > + /* > + * Ok we only have 4K HPTE > + */ > + if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1) > + return 0; Except you don't actually support THP on 4K base page size yet. > + > + return 1; > +} > #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ > > pmd_t pmdp_get_and_clear(struct mm_struct *mm,
David Gibson <dwg@au1.ibm.com> writes: > On Mon, Apr 29, 2013 at 01:21:49AM +0530, Aneesh Kumar K.V wrote: >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> >> >> We enable only if the we support 16MB page size. >> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> >> --- >> arch/powerpc/include/asm/pgtable-ppc64.h | 3 +-- >> arch/powerpc/mm/pgtable_64.c | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 29 insertions(+), 2 deletions(-) >> >> diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h >> index 97fc839..d65534b 100644 >> --- a/arch/powerpc/include/asm/pgtable-ppc64.h >> +++ b/arch/powerpc/include/asm/pgtable-ppc64.h >> @@ -426,8 +426,7 @@ static inline unsigned long pmd_pfn(pmd_t pmd) >> return pmd_val(pmd) >> PTE_RPN_SHIFT; >> } >> >> -/* We will enable it in the last patch */ >> -#define has_transparent_hugepage() 0 >> +extern int has_transparent_hugepage(void); >> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ >> >> static inline int pmd_young(pmd_t pmd) >> diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c >> index 54216c1..b742d6f 100644 >> --- a/arch/powerpc/mm/pgtable_64.c >> +++ b/arch/powerpc/mm/pgtable_64.c >> @@ -754,6 +754,34 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, >> return; >> } >> >> +int has_transparent_hugepage(void) >> +{ >> + if (!mmu_has_feature(MMU_FTR_16M_PAGE)) >> + return 0; >> + /* >> + * We support THP only if HPAGE_SHIFT is 16MB. >> + */ >> + if (!HPAGE_SHIFT || (HPAGE_SHIFT != mmu_psize_defs[MMU_PAGE_16M].shift)) >> + return 0; > > Again, THP should not be dependent on the value of HPAGE_SHIFT. Just > checking that mmu_psize_defsz[MMU_PAGE_16M].shift == 24 should be > sufficient (i.e. that 16M hugepages are supported). done + /* + * We support THP only if PMD_SIZE is 16MB. + */ + if (mmu_psize_defs[MMU_PAGE_16M].shift != PMD_SHIFT) + return 0; + /* > >> + /* >> + * We need to make sure that we support 16MB hugepage in a segement >> + * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE >> + * of 64K. >> + */ >> + /* >> + * If we have 64K HPTE, we will be using that by default >> + */ >> + if (mmu_psize_defs[MMU_PAGE_64K].shift && >> + (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1)) >> + return 0; >> + /* >> + * Ok we only have 4K HPTE >> + */ >> + if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1) >> + return 0; > > Except you don't actually support THP on 4K base page size yet. That is 64K linux page size and 4K HPTE . We do support that. The Linux page size part is taken care by Kconfig. > >> + >> + return 1; >> +} >> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ >> >> pmd_t pmdp_get_and_clear(struct mm_struct *mm, > -aneesh
On Sat, May 04, 2013 at 12:19:03AM +0530, Aneesh Kumar K.V wrote: > David Gibson <dwg@au1.ibm.com> writes: > > > On Mon, Apr 29, 2013 at 01:21:49AM +0530, Aneesh Kumar K.V wrote: > >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> > >> > >> We enable only if the we support 16MB page size. > >> > >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> > >> --- > >> arch/powerpc/include/asm/pgtable-ppc64.h | 3 +-- > >> arch/powerpc/mm/pgtable_64.c | 28 ++++++++++++++++++++++++++++ > >> 2 files changed, 29 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h > >> index 97fc839..d65534b 100644 > >> --- a/arch/powerpc/include/asm/pgtable-ppc64.h > >> +++ b/arch/powerpc/include/asm/pgtable-ppc64.h > >> @@ -426,8 +426,7 @@ static inline unsigned long pmd_pfn(pmd_t pmd) > >> return pmd_val(pmd) >> PTE_RPN_SHIFT; > >> } > >> > >> -/* We will enable it in the last patch */ > >> -#define has_transparent_hugepage() 0 > >> +extern int has_transparent_hugepage(void); > >> #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ > >> > >> static inline int pmd_young(pmd_t pmd) > >> diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c > >> index 54216c1..b742d6f 100644 > >> --- a/arch/powerpc/mm/pgtable_64.c > >> +++ b/arch/powerpc/mm/pgtable_64.c > >> @@ -754,6 +754,34 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, > >> return; > >> } > >> > >> +int has_transparent_hugepage(void) > >> +{ > >> + if (!mmu_has_feature(MMU_FTR_16M_PAGE)) > >> + return 0; > >> + /* > >> + * We support THP only if HPAGE_SHIFT is 16MB. > >> + */ > >> + if (!HPAGE_SHIFT || (HPAGE_SHIFT != mmu_psize_defs[MMU_PAGE_16M].shift)) > >> + return 0; > > > > Again, THP should not be dependent on the value of HPAGE_SHIFT. Just > > checking that mmu_psize_defsz[MMU_PAGE_16M].shift == 24 should be > > sufficient (i.e. that 16M hugepages are supported). > > done > > + /* > + * We support THP only if PMD_SIZE is 16MB. > + */ > + if (mmu_psize_defs[MMU_PAGE_16M].shift != PMD_SHIFT) > + return 0; > + /* Much better. > >> + /* > >> + * We need to make sure that we support 16MB hugepage in a segement > >> + * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE > >> + * of 64K. > >> + */ > >> + /* > >> + * If we have 64K HPTE, we will be using that by default > >> + */ > >> + if (mmu_psize_defs[MMU_PAGE_64K].shift && > >> + (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1)) > >> + return 0; > >> + /* > >> + * Ok we only have 4K HPTE > >> + */ > >> + if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1) > >> + return 0; > > > > Except you don't actually support THP on 4K base page size yet. > > > That is 64K linux page size and 4K HPTE . We do support that. Good point, sorry.
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h index 97fc839..d65534b 100644 --- a/arch/powerpc/include/asm/pgtable-ppc64.h +++ b/arch/powerpc/include/asm/pgtable-ppc64.h @@ -426,8 +426,7 @@ static inline unsigned long pmd_pfn(pmd_t pmd) return pmd_val(pmd) >> PTE_RPN_SHIFT; } -/* We will enable it in the last patch */ -#define has_transparent_hugepage() 0 +extern int has_transparent_hugepage(void); #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ static inline int pmd_young(pmd_t pmd) diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index 54216c1..b742d6f 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -754,6 +754,34 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, return; } +int has_transparent_hugepage(void) +{ + if (!mmu_has_feature(MMU_FTR_16M_PAGE)) + return 0; + /* + * We support THP only if HPAGE_SHIFT is 16MB. + */ + if (!HPAGE_SHIFT || (HPAGE_SHIFT != mmu_psize_defs[MMU_PAGE_16M].shift)) + return 0; + /* + * We need to make sure that we support 16MB hugepage in a segement + * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE + * of 64K. + */ + /* + * If we have 64K HPTE, we will be using that by default + */ + if (mmu_psize_defs[MMU_PAGE_64K].shift && + (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1)) + return 0; + /* + * Ok we only have 4K HPTE + */ + if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1) + return 0; + + return 1; +} #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ pmd_t pmdp_get_and_clear(struct mm_struct *mm,