| Message ID | 1362732066-8056-2-git-send-email-Gang.Liu@freescale.com |
|---|---|
| State | Superseded, archived |
| Delegated to: | Andy Fleming |
| Headers | show |
On Fri, Mar 8, 2013 at 2:41 AM, Liu Gang <Gang.Liu@freescale.com> wrote: > Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to > "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from > arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros > in configuration header file of each board which can support the > master module of Boot from SRIO and PCIE. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > More important than explaining what the patch does is explaining *why*. Why was this change necessary? Make sure the "why" includes what makes this feature a board feature, as opposed to an SoC feature? Andy
On Tue, 2013-04-30 at 17:28 -0500, Andy Fleming wrote: > On Fri, Mar 8, 2013 at 2:41 AM, Liu Gang <Gang.Liu@freescale.com> > wrote: > Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to > "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from > arch/powerpc/include/asm/config_mpc85xx.h file, and add those > macros > in configuration header file of each board which can support > the > master module of Boot from SRIO and PCIE. > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > > > > > More important than explaining what the patch does is explaining > *why*. Why was this change necessary? > > > Make sure the "why" includes what makes this feature a board feature, > as opposed to an SoC feature? > > > Andy Thanks, I'll updated the commit message. And in addition, why the state of the below patch is superseded? http://patchwork.ozlabs.org/patch/226046/
York has submitted a bunch of patches. I marked yours as superseded to note that I'll take his copy. There are others like that, but I'm holding off on deciding which copy to take until I can review them. On Sun, May 5, 2013 at 10:28 PM, Liu Gang <Gang.Liu@freescale.com> wrote: > On Tue, 2013-04-30 at 17:28 -0500, Andy Fleming wrote: > > > > On Fri, Mar 8, 2013 at 2:41 AM, Liu Gang <Gang.Liu@freescale.com> > > wrote: > > Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to > > "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from > > arch/powerpc/include/asm/config_mpc85xx.h file, and add those > > macros > > in configuration header file of each board which can support > > the > > master module of Boot from SRIO and PCIE. > > > > Signed-off-by: Liu Gang <Gang.Liu@freescale.com> > > > > > > > > > > More important than explaining what the patch does is explaining > > *why*. Why was this change necessary? > > > > > > Make sure the "why" includes what makes this feature a board feature, > > as opposed to an SoC feature? > > > > > > Andy > Thanks, I'll updated the commit message. > And in addition, why the state of the below patch is superseded? > http://patchwork.ozlabs.org/patch/226046/ > > > >
On Mon, 2013-05-06 at 13:58 -0500, Andy Fleming wrote: > York has submitted a bunch of patches. I marked yours as superseded to > note that I'll take his copy. There are others like that, but I'm > holding off on deciding which copy to take until I can review them. > Yes, I have known those patches about this feature in York's list, and pointed out to York and you. I transferred that mail to you, please find it. In addition, my patches about this feature have some updates compared with York's list, so please apply my patches for this feature, thanks! And I have sent the patches for version 2 based on your comments. Thanks a lot! Liu Gang
diff --git a/README b/README index 42544ce..a749094 100644 --- a/README +++ b/README @@ -3706,6 +3706,9 @@ Low Level (hardware related) configuration options: - CONFIG_SRIO2: Board has SRIO 2 port available +- CONFIG_SRIO_PCIE_BOOT_MASTER + Board can support master function for Boot from SRIO and PCIE + - CONFIG_SYS_SRIOn_MEM_VIRT: Virtual Address of SRIO port 'n' memory region diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index de9d916..d860eba 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -564,7 +564,7 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER char *s = getenv("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 6e6f7dc..90d1065 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -24,7 +24,7 @@ #include <asm/fsl_srio.h> #include <asm/errno.h> -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 @@ -299,7 +299,7 @@ void srio_init(void) } } -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d57c178..51daf80 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -335,7 +335,6 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -367,7 +366,6 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -409,7 +407,6 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -443,7 +440,6 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 -#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 77ac1f7..621c899 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER static void fsl_pcie_boot_master(pit_t *pi) { /* configure inbound window for slave's u-boot image */ @@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ char *s = getenv("bootmaster"); char pcie[6]; @@ -624,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; -#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER } else { /* boot from PCIE --master releases slave's core 0 */ char *s = getenv("bootmaster"); diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index bbc53ce..ebef17f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -77,6 +77,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_FSL_LAW /* Use common FSL init code */ diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index ce8f9b0..dd2b9c3 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -40,7 +40,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 53979dd..48acee4 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -36,7 +36,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 778230d..d1e27c4 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ - +#define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #include "corenet_ds.h"
Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> --- README | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 4 ++-- arch/powerpc/include/asm/config_mpc85xx.h | 4 ---- drivers/pci/fsl_pci_init.c | 6 +++--- include/configs/P2041RDB.h | 1 + include/configs/P3041DS.h | 2 +- include/configs/P4080DS.h | 2 +- include/configs/P5020DS.h | 2 +- 9 files changed, 13 insertions(+), 13 deletions(-)