diff mbox

[AArch64] Compare instruction in shift_extend mode

Message ID a6adc1ade69444ea98ebf361027b749f@SN2PR07MB029.namprd07.prod.outlook.com
State New
Headers show

Commit Message

Hurugalawadi, Naveen April 15, 2013, 4:37 a.m. UTC 
Hi,

>> Same issue as my previous reply applies here.

Thanks for the suggestion.

Please find attached the modified patch as per your suggestions.
Please review the same and let me know if there should be any 
further modifications in it.

Thanks,
Naveen

Comments

Marcus Shawcroft April 16, 2013, 1:57 p.m. UTC | #1 
On 15/04/13 05:37, Hurugalawadi, Naveen wrote:
> Hi,
>
>>> Same issue as my previous reply applies here.
>
> Thanks for the suggestion.
>
> Please find attached the modified patch as per your suggestions.
> Please review the same and let me know if there should be any
> further modifications in it.
>
> Thanks,
> Naveen
>


Hi,

The .md pattern looks OK.  I'm not happy about the test case.  It is too 
fragile.  For example, adding -fno-inline such that main does not get 
optimized away breaks the pattern match.  When we run the testsuites 
here we often do a run with -fPIC in order to increase coverage, that 
option will also break this test case.  I suggest for this one test case 
either making it compile only and dropping main() such that the pattern 
match only looks in the assembled output of the cmp_* functions, or 
leaving the test case execute but removing the pattern match...

Cheers
/Marcus
diff mbox

Patch

--- gcc/config/aarch64/aarch64.md	2013-04-15 09:41:29.711014628 +0530
+++ gcc/config/aarch64/aarch64.md	2013-04-15 09:51:08.027015641 +0530
@@ -2205,6 +2205,18 @@ 
    (set_attr "mode" "<GPI:MODE>")]
 )
 
+(define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>"
+  [(set (reg:CC_SWP CC_REGNUM)
+	(compare:CC_SWP (ashift:GPI
+			 (ANY_EXTEND:GPI
+			  (match_operand:ALLX 0 "register_operand" "r"))
+			 (match_operand:QI 1 "aarch64_shift_imm_<mode>" "n"))
+	(match_operand:GPI 2 "register_operand" "r")))]
+  ""
+  "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
+  [(set_attr "v8type" "alus_ext")
+   (set_attr "mode" "<GPI:MODE>")]
+)
 
 ;; -------------------------------------------------------------------
 ;; Store-flag and conditional select insns
--- gcc/testsuite/gcc.target/aarch64/cmp.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/cmp.c	2013-04-15 09:54:29.471015995 +0530
@@ -0,0 +1,135 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+  if (((s64)a << 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = cmp_si_test1 (2, 12, 5);
+  if (x != 19)
+    abort ();
+
+  x = cmp_si_test1 (1, 2, 32);
+  if (x != 35)
+    abort ();
+
+  x = cmp_si_test2 (7, 5, 15);
+  if (x != 27)
+    abort ();
+
+  x = cmp_si_test2 (12, 1, 3);
+  if (x != 16)
+    abort ();
+
+  y = cmp_di_test1 (0x20202020ll,
+		    0x65161611ll,
+		    0x42434243ll);
+  if (y != 0xc7797874ll)
+    abort ();
+
+  y = cmp_di_test1 (0x1010101010101ll,
+		    0x123456789abcdll,
+		    0x5555555555555ll);
+  if (y != 0x7799bbde00223ll)
+    abort ();
+
+  y = cmp_di_test2 (0x31313131ll,
+		    0x35466561ll,
+		    0x42434243ll);
+  if (y != 0xa8bad8d5ll)
+    abort ();
+
+  y = cmp_di_test2 (0x101010101ll,
+		    0x123456789ll,
+		    0x555555555ll);
+  if (y != 0x7799bbddfll)
+    abort ();
+
+  x = cmp_di_test3 (6252,
+                    0x64234978ll,
+                    0x12345123ll);
+  if (x != 1985458951)
+    abort ();
+
+  x = cmp_di_test3 (7635,
+                    0x10101010ll,
+                    0x21212121ll);
+  if (x != 825315076)
+    abort ();
+
+  x = cmp_di_test4 (202,
+                    0x984210421ll,
+                    0x18181818181ll);
+  if (x != 94537324)
+    abort ();
+
+  x = cmp_di_test4 (167,
+                    0x987987987987ll,
+                    0x12312312ll);
+  if (x != -1714840256)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */