| Message ID | 1364500442-20927-5-git-send-email-Varun.Sethi@freescale.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Kumar Gala |
| Headers | show |
On Fri, Mar 29, 2013 at 01:24:01AM +0530, Varun Sethi wrote: > +/* cache stash targets */ > +enum stash_target { > + IOMMU_ATTR_CACHE_L1 = 1, > + IOMMU_ATTR_CACHE_L2, > + IOMMU_ATTR_CACHE_L3, > +}; > + > +/* This attribute corresponds to IOMMUs capable of generating > + * a stash transaction. A stash transaction is typically a > + * hardware initiated prefetch of data from memory to cache. > + * This attribute allows configuring stashig specific parameters > + * in the IOMMU hardware. > + */ > + > +struct iommu_stash_attribute { > + u32 cpu; /* cpu number */ > + u32 cache; /* cache to stash to: L1,L2,L3 */ > +}; > + I would prefer these PAMU specific enum and struct to be in a pamu-specific iommu-header. Joerg
> -----Original Message----- > From: Joerg Roedel [mailto:joro@8bytes.org] > Sent: Tuesday, April 02, 2013 8:40 PM > To: Sethi Varun-B16395 > Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux- > foundation.org; linuxppc-dev@lists.ozlabs.org; linux- > kernel@vger.kernel.org; galak@kernel.crashing.org; > benh@kernel.crashing.org > Subject: Re: [PATCH 4/5 v11] iommu/fsl: Add additional iommu attributes > required by the PAMU driver. > > On Fri, Mar 29, 2013 at 01:24:01AM +0530, Varun Sethi wrote: > > +/* cache stash targets */ > > +enum stash_target { > > + IOMMU_ATTR_CACHE_L1 = 1, > > + IOMMU_ATTR_CACHE_L2, > > + IOMMU_ATTR_CACHE_L3, > > +}; > > + > > +/* This attribute corresponds to IOMMUs capable of generating > > + * a stash transaction. A stash transaction is typically a > > + * hardware initiated prefetch of data from memory to cache. > > + * This attribute allows configuring stashig specific parameters > > + * in the IOMMU hardware. > > + */ > > + > > +struct iommu_stash_attribute { > > + u32 cpu; /* cpu number */ > > + u32 cache; /* cache to stash to: L1,L2,L3 */ > > +}; > > + > > I would prefer these PAMU specific enum and struct to be in a pamu- > specific iommu-header. > [Sethi Varun-B16395] But, these would be used by the IOMMU API users (e.g. VFIO), they shouldn't depend on PAMU specific headers. -Varun
On Wed, Apr 03, 2013 at 05:21:16AM +0000, Sethi Varun-B16395 wrote: > > I would prefer these PAMU specific enum and struct to be in a pamu- > > specific iommu-header. > > > > [Sethi Varun-B16395] But, these would be used by the IOMMU API users > (e.g. VFIO), they shouldn't depend on PAMU specific headers. Drivers that use PAMU specifics (like the PAMU specific VFIO parts) can also include the PAMU specific header. Joerg
diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 2727810..af8f996 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -40,6 +40,25 @@ struct notifier_block; typedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, unsigned long, int, void *); +/* cache stash targets */ +enum stash_target { + IOMMU_ATTR_CACHE_L1 = 1, + IOMMU_ATTR_CACHE_L2, + IOMMU_ATTR_CACHE_L3, +}; + +/* This attribute corresponds to IOMMUs capable of generating + * a stash transaction. A stash transaction is typically a + * hardware initiated prefetch of data from memory to cache. + * This attribute allows configuring stashig specific parameters + * in the IOMMU hardware. + */ + +struct iommu_stash_attribute { + u32 cpu; /* cpu number */ + u32 cache; /* cache to stash to: L1,L2,L3 */ +}; + struct iommu_domain_geometry { dma_addr_t aperture_start; /* First address that can be mapped */ dma_addr_t aperture_end; /* Last address that can be mapped */ @@ -57,10 +76,26 @@ struct iommu_domain { #define IOMMU_CAP_CACHE_COHERENCY 0x1 #define IOMMU_CAP_INTR_REMAP 0x2 /* isolates device intrs */ +/* + * Following constraints are specifc to PAMUV1: + * -aperture must be power of 2, and naturally aligned + * -number of windows must be power of 2, and address space size + * of each window is determined by aperture size / # of windows + * -the actual size of the mapped region of a window must be power + * of 2 starting with 4KB and physical address must be naturally + * aligned. + * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. + * The caller can invoke iommu_domain_get_attr to check if the underlying + * iommu implementation supports these constraints. + */ + enum iommu_attr { DOMAIN_ATTR_GEOMETRY, DOMAIN_ATTR_PAGING, DOMAIN_ATTR_WINDOWS, + DOMAIN_ATTR_PAMU_STASH, + DOMAIN_ATTR_PAMU_ENABLE, + DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_MAX, };
Added the following domain attributes for the FSL PAMU driver: 1. Added new iommu stash attribute, which allows setting of the LIODN specific stash id parameter through IOMMU API. 2. Added an attribute for enabling/disabling DMA to a particular memory window. 3. Added domain attribute to check for PAMUV1 specific constraints. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> --- - no change in v11. - no change in v10. include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-)