| Message ID | 1362751245-32432-1-git-send-email-ldewangan@nvidia.com |
|---|---|
| State | Rejected, archived |
| Headers | show |
On 03/08/2013 07:00 AM, Laxman Dewangan wrote: > UARTB clock bit in CAR register is 7. Correcting this > in DTS file. The register bit is 7, but the clock ID in the Tegra CAR DT binding is 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and 2 separate IP block reset bits, or the other way around, so we highlight the issue by assigning different clock IDs. See the comment before the list of clock IDs in the binding document. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Friday 08 March 2013 11:17 PM, Stephen Warren wrote: > On 03/08/2013 07:00 AM, Laxman Dewangan wrote: >> UARTB clock bit in CAR register is 7. Correcting this >> in DTS file. > The register bit is 7, but the clock ID in the Tegra CAR DT binding is > 96 for UART2 or 97 for VFIR. This was due to there being 1 clock bit and > 2 separate IP block reset bits, or the other way around, so we highlight > the issue by assigning different clock IDs. See the comment before the > list of clock IDs in the binding document. Aaha, I missed the Documentation part. I was looking for DT entry only found this. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index bbbe2de..b89fea2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -260,7 +260,7 @@ reg-shift = <2>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 96>; + clocks = <&tegra_car 7>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index eddd0f9..0c9532b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -247,7 +247,7 @@ reg-shift = <2>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 160>; + clocks = <&tegra_car 7>; status = "disabled"; };
UARTB clock bit in CAR register is 7. Correcting this in DTS file. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> --- arch/arm/boot/dts/tegra20.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)