Message ID | alpine.LRH.2.00.0901301334220.13283@vixen.sonytel.be (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show |
> | PCI host bridge /plb/pci@1ec000000 (primary) ranges: > | MEM 0x0000000180000000..0x00000001bfffffff -> 0x0000000080000000 > | IO 0x00000001e8000000..0x00000001e800ffff -> 0x0000000000000000 > | IO 0x00000001e8800000..0x00000001ebffffff -> 0x0000000000000000 > | \--> Skipped (too many) ! > | 4xx PCI DMA offset set to 0x00000000 > | ppc4xx_configure_pci_PMMs: i = 0, hose->pci_mem_offset = 0x100000000 > | ppc4xx_setup_one_pci_PMM: hose = 0xcf825000 > | ppc4xx_setup_one_pci_PMM: reg = 0xd1000000 > | ppc4xx_setup_one_pci_PMM: plb_addr = 0x180000000 > | ppc4xx_setup_one_pci_PMM: pci_addr = 0x80000000 > | ppc4xx_setup_one_pci_PMM: size = 0x40000000 > | ppc4xx_setup_one_pci_PMM: flags = 0x200 > | ppc4xx_setup_one_pci_PMM: index = 0 > | /plb/pci@1ec000000: Resource out of range > ^^^^^^^^^^^^^^^^^^^^^ > because plb_addr + size lies outside 32-bit space. Ok so the code was buggy already, the ISA hole patch just makes it trigger... For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the PCI-E), we only know how to program 32-bit of PLB address. IE. The old code would have cropped the plb_addr when writing to the register, the new code complains. I suspect some implementation support a register to put the "high" part of the PLB address, and that it already contains 1, so the old code would have worked by chance, the new code doesn't because it bails out. I need to check the doco for your CPU or any other using that cell to see who supports what regarding the location of the outbound windows in PLB space. I think the original 440GP which I used as a basis for the PCI 2.x host bridge only supports 32-bits here but maybe I'm just confused. I'll have a look next week. Cheers, Ben
> For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the > PCI-E), we only know how to program 32-bit of PLB address. IE. The old > code would have cropped the plb_addr when writing to the register, the > new code complains. > > I suspect some implementation support a register to put the "high" part > of the PLB address, and that it already contains 1, so the old code > would have worked by chance, the new code doesn't because it bails out. Hrm... from the doco it's also one 32-bit register... I'm starting to think that those guys always assume the top 1 bit is set or something like that ... The doc is unclear. Maybe somebody form AMCC can confirm ? Cheers, Ben.
Hi: It looks like the top bit is hard coded to 1. There doesn't seem to be anyway Of changing it. Feng Kan AMCC Engineering -----Original Message----- From: linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org [mailto:linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org] On Behalf Of Benjamin Herrenschmidt Sent: Friday, January 30, 2009 1:30 PM To: Geert Uytterhoeven Cc: Linux/PPC Development Subject: Re: Broken PCI on Sequoia > For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the > PCI-E), we only know how to program 32-bit of PLB address. IE. The old > code would have cropped the plb_addr when writing to the register, the > new code complains. > > I suspect some implementation support a register to put the "high" part > of the PLB address, and that it already contains 1, so the old code > would have worked by chance, the new code doesn't because it bails out. Hrm... from the doco it's also one 32-bit register... I'm starting to think that those guys always assume the top 1 bit is set or something like that ... The doc is unclear. Maybe somebody form AMCC can confirm ? Cheers, Ben.
On Fri, 2009-01-30 at 17:19 -0800, Feng Kan wrote: > Hi: > It looks like the top bit is hard coded to 1. There doesn't seem to > be anyway > Of changing it. Thanks ! Would it be possible for you to check other 4xx parts using that PCI controller as to whether the top bit is always hard-coded to 1 or it changes from part to part ? Thanks ! Cheers, Ben. > Feng Kan > AMCC Engineering > > -----Original Message----- > From: linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org > [mailto:linuxppc-dev-bounces+fkan=amcc.com@ozlabs.org] On Behalf Of > Benjamin Herrenschmidt > Sent: Friday, January 30, 2009 1:30 PM > To: Geert Uytterhoeven > Cc: Linux/PPC Development > Subject: Re: Broken PCI on Sequoia > > > > For that sort of 4xx PHB (ie, the PCI 2.x ones, not the PCI-X nor the > > PCI-E), we only know how to program 32-bit of PLB address. IE. The old > > code would have cropped the plb_addr when writing to the register, the > > new code complains. > > > > I suspect some implementation support a register to put the "high" > part > > of the PLB address, and that it already contains 1, so the old code > > would have worked by chance, the new code doesn't because it bails > out. > > Hrm... from the doco it's also one 32-bit register... I'm starting to > think that those guys always assume the top 1 bit is set or something > like that ... > > The doc is unclear. Maybe somebody form AMCC can confirm ? > > Cheers, > Ben. > > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@ozlabs.org > https://ozlabs.org/mailman/listinfo/linuxppc-dev
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c index 77fae5f..70684ee 100644 --- a/arch/powerpc/sysdev/ppc4xx_pci.c +++ b/arch/powerpc/sysdev/ppc4xx_pci.c @@ -16,6 +16,8 @@ * */ +#define pr_fmt(fmt) "%s: " fmt, __func__ + #undef DEBUG #include <linux/kernel.h> @@ -204,6 +206,13 @@ static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, { u32 ma, pcila, pciha; +pr_info(" hose = 0x%p\n", hose); +pr_info(" reg = 0x%p\n", reg); +pr_info(" plb_addr = 0x%llx\n", plb_addr); +pr_info(" pci_addr = 0x%llx\n", pci_addr); +pr_info(" size = 0x%llx\n", size); +pr_info(" flags = 0x%x\n", flags); +pr_info(" index = %d\n", index); if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || size < 0x1000 || (plb_addr & (size - 1)) != 0) { printk(KERN_WARNING "%s: Resource out of range\n", @@ -244,6 +253,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, } /* Configure the resource */ +pr_info("i = %d, hose->pci_mem_offset = 0x%llx\n", i, hose->pci_mem_offset); if (ppc4xx_setup_one_pci_PMM(hose, reg, res->start, res->start - hose->pci_mem_offset, @@ -260,6 +270,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, } } +pr_info("hose->isa_mem_phys = 0x%llx, hose->isa_mem_size = 0x%llx\n", hose->isa_mem_phys, hose->isa_mem_size); /* Handle ISA memory hole if not already covered */ if (j <= 2 && !found_isa_hole && hose->isa_mem_size) if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,