| Message ID | 1360961665-10693-4-git-send-email-benoit.thebaudeau@advansee.com |
|---|---|
| State | Superseded |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Benoit, On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau <benoit.thebaudeau@advansee.com> wrote: > Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB > pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. > > eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this > board, which satisfies the 30-ns NF R/W cycle requirement. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> NAND is not detected on my mx53ard. I think we need to adjust the IOMUX as per: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx53_ard/mx53_ard.c?h=imx_v2009.08 Regards, Fabio Estevam
On Tue, Feb 26, 2013 at 10:22 AM, Fabio Estevam <festevam@gmail.com> wrote: > Hi Benoit, > > On Fri, Feb 15, 2013 at 6:54 PM, Benoît Thébaudeau > <benoit.thebaudeau@advansee.com> wrote: >> Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB >> pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. >> >> eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this >> board, which satisfies the 30-ns NF R/W cycle requirement. >> >> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > > NAND is not detected on my mx53ard. > > I think we need to adjust the IOMUX as per: > http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/board/freescale/mx53_ard/mx53_ard.c?h=imx_v2009.08 Yes, after using the same IOMUX from FSL U-boot I get: NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB .... MX53ARD U-Boot > nand info Device 0: NAND 2GiB 3,3V 8-bit, sector size 256 KiB Page size 2048 b OOB size 64 b Erase size 262144 b MX53ARD U-Boot >
Hi Benoît, On Tue, Feb 26, 2013 at 10:35 AM, Fabio Estevam <festevam@gmail.com> wrote: > Yes, after using the same IOMUX from FSL U-boot I get: > > NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB 3,3) > NAND bus width 16 instead 8 bit > No NAND device found!!! > 0 MiB This should be fixed separetely and it is not related to your patch. I will submit a patch for this 16-bit detection issue I was able to read and write to NAND, I have also tested to save env vars into NAND and it works fine. So, after changing the IOMUX as per FSL U-boot you can add my: Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Hi Fabio, On Tuesday, February 26, 2013 3:21:25 PM, Fabio Estevam wrote: > Hi Benoît, > > On Tue, Feb 26, 2013 at 10:35 AM, Fabio Estevam <festevam@gmail.com> wrote: > > > Yes, after using the same IOMUX from FSL U-boot I get: > > > > NAND: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd5 (Samsung NAND 2GiB > > 3,3) > > NAND bus width 16 instead 8 bit > > No NAND device found!!! > > 0 MiB > > This should be fixed separetely and it is not related to your patch. I > will submit a patch for this 16-bit detection issue OK. Please update all boards using mxc_nand. > I was able to read and write to NAND, I have also tested to save env > vars into NAND and it works fine. Great! Thanks for testing. > So, after changing the IOMUX as per FSL U-boot If I look at FSL's setup_nfc() vs. my setup_iomux_nand(): - The IOMUX setup is the same, with CS1 and DA0-7 left in their reset ALT0 mode. - The pad setups differ from the reset values in FSL's code, so I think that this is all that needs to be changed (i.e. adding the mxc_iomux_set_pad()). Can you confirm? - Are 'M4IF_GPR.MM = 0' and 'EIM_CSxGCR2[12] = 0' also required, or is this handled properly by your board through BOOT_CFG1[6]? I think that we should enforce this too by software for the same reason as for bus width. > you can add my: > Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Will do, thanks again. So for 01-03, and 15 (with 0x32000). Do you agree? Best regards, Benoît
On Tue, Feb 26, 2013 at 1:53 PM, Benoît Thébaudeau <benoit.thebaudeau@advansee.com> wrote: > OK. Please update all boards using mxc_nand. Yes, will send a patch soon. >> I was able to read and write to NAND, I have also tested to save env >> vars into NAND and it works fine. > > Great! Thanks for testing. > >> So, after changing the IOMUX as per FSL U-boot > > If I look at FSL's setup_nfc() vs. my setup_iomux_nand(): > - The IOMUX setup is the same, with CS1 and DA0-7 left in their reset ALT0 > mode. > - The pad setups differ from the reset values in FSL's code, so I think that > this is all that needs to be changed (i.e. adding the mxc_iomux_set_pad()). > Can you confirm? Yes, correct. > - Are 'M4IF_GPR.MM = 0' and 'EIM_CSxGCR2[12] = 0' also required, or is this > handled properly by your board through BOOT_CFG1[6]? I think that we should > enforce this too by software for the same reason as for bus width. Yes, we need to enforce this by software. If I skip such settings, NAND is no longer functional on mx53ard. >> you can add my: >> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> > > Will do, thanks again. So for 01-03, and 15 (with 0x32000). Do you agree? Yes, correct. Very good job you did, thanks!
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2fc8570..8907388 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -58,6 +58,23 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +#ifdef CONFIG_NAND_MXC +static void setup_iomux_nand(void) +{ + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); +} +#else +static void setup_iomux_nand(void) +{ +} +#endif + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -277,6 +294,7 @@ static void weim_cs1_settings(void) int board_early_init_f(void) { + setup_iomux_nand(); setup_iomux_uart(); return 0; } diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 62cb42b..148f7a2 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -41,6 +41,16 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_NAND + #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE
Add support for the Samsung K9LAG08U0M NAND Flash (2-GiB MLC NAND Flash, 2-kiB pages, 256-kiB blocks, 30-ns R/W cycles, 1 CS) on mx53ard. eNFC_CLK_ROOT is set up with a cycle time of 37.5 ns (400 MHz / 3 / 5) for this board, which satisfies the 30-ns NF R/W cycle requirement. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> --- Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: - New patch. Changes in v2: None board/freescale/mx53ard/mx53ard.c | 18 ++++++++++++++++++ include/configs/mx53ard.h | 10 ++++++++++ 2 files changed, 28 insertions(+)