Message ID | 20130219222642.GA23888@code-monkey.de |
---|---|
State | New |
Headers | show |
Tilman Sauerbeck [2013-02-19 23:26]: > However it breaks the case where the 2nd operand is a const_int that > *can* be used as an immediate (eg 0x80), and ends up generating the > AND/CMP combination. ... and that would be because I changed the operand patterns in zeroextractsi_compare0_scratch and didn't restore the originals when trying the new diff :/ So the diff I posted last night might do the trick. If there's no obvious reason why it would be wrong, I'll start a bootstrap and regression test tonight. Thanks, Tilman
On 19/02/13 22:26, Tilman Sauerbeck wrote: > I don't get why relaxing the restrictions for the > andsi3_compare0_scratch pattern results in a mismatch for the > zeroextractsi_compare0_scratch one. > > Any ideas? Because of the way combine works. It first tries to find a pattern that doesn't have a clobber expression. It finds your new pattern and then uses that. But since that can't handle immediates, reload then comes along and forces the constant into a register. You need one pattern to deal with all the cases. R.
Richard Earnshaw [2013-02-20 11:00]: > On 19/02/13 22:26, Tilman Sauerbeck wrote: > >I don't get why relaxing the restrictions for the > >andsi3_compare0_scratch pattern results in a mismatch for the > >zeroextractsi_compare0_scratch one. > > > >Any ideas? > > Because of the way combine works. It first tries to find a pattern that > doesn't have a clobber expression. It finds your new pattern and then uses > that. But since that can't handle immediates, reload then comes along and > forces the constant into a register. > > You need one pattern to deal with all the cases. You mean the pattern should include calls to arm_split_constant() to do the loading itself, like e.g. the iorsi3 pattern does? Why can't we let reload do the load? FWIW the patch in http://gcc.gnu.org/ml/gcc-patches/2013-02/msg00920.html works for my testcases, survives a bootstrap in qemu and passes the test suite (I only built/tested the C and C++ frontends though). Thanks, Tilman
Tilman Sauerbeck [2013-02-24 17:00]: > Richard Earnshaw [2013-02-20 11:00]: > > On 19/02/13 22:26, Tilman Sauerbeck wrote: > > >I don't get why relaxing the restrictions for the > > >andsi3_compare0_scratch pattern results in a mismatch for the > > >zeroextractsi_compare0_scratch one. > > > > > >Any ideas? > > > > Because of the way combine works. It first tries to find a pattern that > > doesn't have a clobber expression. It finds your new pattern and then uses > > that. But since that can't handle immediates, reload then comes along and > > forces the constant into a register. > > > > You need one pattern to deal with all the cases. > > You mean the pattern should include calls to arm_split_constant() to do > the loading itself, like e.g. the iorsi3 pattern does? > Why can't we let reload do the load? > > FWIW the patch in http://gcc.gnu.org/ml/gcc-patches/2013-02/msg00920.html > works for my testcases, survives a bootstrap in qemu and passes the > test suite (I only built/tested the C and C++ frontends though). Sorry to be a pain, but ... ping? I don't know how to proceed with this patch. Thanks. Regards, Tilman
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 64888f9..3724a8d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2200,7 +2200,7 @@ [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") - (match_operand:SI 1 "arm_not_operand" "I,K,r")) + (match_operand:SI 1 "reg_or_int_operand" "I,K,r")) (const_int 0))) (clobber (match_scratch:SI 2 "=X,r,X"))] "TARGET_32BIT"