| Message ID | 1359075633-13502-5-git-send-email-dinguyen@altera.com |
|---|---|
| State | New |
| Headers | show |
On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > mach-socfpga is another platform that needs to use > v7_invalidate_l1 to bringup additional cores. There was a comment that > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Olof Johansson <olof@lixom.net> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Rob Herring <rob.herring@calxeda.com> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Simon Horman <horms@verge.net.au> > Cc: Magnus Damm <magnus.damm@gmail.com> > Cc: Stephen Warren <swarren@wwwdotorg.org> > Cc: Pavel Machek <pavel@denx.de> mach-shmobile portion: Acked-by: Simon Horman <horms+renesas@verge.net.au>
On Fri, Jan 25, 2013 at 01:15:03PM +0900, Simon Horman wrote: > On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen@altera.com wrote: > > From: Dinh Nguyen <dinguyen@altera.com> > > > > mach-socfpga is another platform that needs to use > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > > Cc: Arnd Bergmann <arnd@arndb.de> > > Cc: Russell King <linux@arm.linux.org.uk> > > Cc: Olof Johansson <olof@lixom.net> > > Cc: Thomas Gleixner <tglx@linutronix.de> > > Cc: Rob Herring <rob.herring@calxeda.com> > > Cc: Sascha Hauer <kernel@pengutronix.de> > > Cc: Simon Horman <horms@verge.net.au> > > Cc: Magnus Damm <magnus.damm@gmail.com> > > Cc: Stephen Warren <swarren@wwwdotorg.org> > > Cc: Pavel Machek <pavel@denx.de> > > mach-shmobile portion: > > Acked-by: Simon Horman <horms+renesas@verge.net.au> For the record, I tested this on the kzm9g, kzm9d and marzen boards.
On 01/24/2013 05:00 PM, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > mach-socfpga is another platform that needs to use > v7_invalidate_l1 to bringup additional cores. There was a comment that > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > -ENTRY(v7_invalidate_l1) > - mov r0, #0 Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that function from headsmp.S to reset-handler.S, so this patch will conflict. How do you want to handle that?
On Friday 25 January 2013 06:30 AM, dinguyen@altera.com wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > mach-socfpga is another platform that needs to use > v7_invalidate_l1 to bringup additional cores. There was a comment that > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Olof Johansson <olof@lixom.net> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Rob Herring <rob.herring@calxeda.com> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Simon Horman <horms@verge.net.au> > Cc: Magnus Damm <magnus.damm@gmail.com> > Cc: Stephen Warren <swarren@wwwdotorg.org> > Cc: Pavel Machek <pavel@denx.de> > --- > arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- > arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- > arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- > arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++++++++++++++ > 4 files changed, 47 insertions(+), 138 deletions(-) > Does yor kernel skips the decompresser. Am just curious about what you describe above since you should see the issue already at decompresser. Your boot loader is expected to clean and invalidating the caches before jumping into the kernel. Regards, Santosh
Hi! > mach-socfpga is another platform that needs to use > v7_invalidate_l1 to bringup additional cores. There was a comment that > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S If there are three copies of code, with fourth one needed for next platform, moving it into common code makes sense. But... The code was not identical before the merge. Are you sure that the differences do not hurt? At the very least, it should be mentioned in the changelog. Thanks, Pavel > diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S > index 7e49deb..921fc15 100644 > --- a/arch/arm/mach-imx/headsmp.S > +++ b/arch/arm/mach-imx/headsmp.S > @@ -17,53 +17,6 @@ > -ENTRY(v7_invalidate_l1) > - mov r0, #0 > - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache > - mcr p15, 2, r0, c0, c0, 0 > - mrc p15, 1, r0, c0, c0, 0 ... > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > index 4a317fa..fb082c4 100644 > --- a/arch/arm/mach-tegra/headsmp.S > +++ b/arch/arm/mach-tegra/headsmp.S > @@ -18,49 +18,6 @@ > -ENTRY(v7_invalidate_l1) > - mov r0, #0 > - mcr p15, 2, r0, c0, c0, 0 > - mrc p15, 1, r0, c0, c0, 0 [Note missing mcr p15, 0, .. line.]
Hi Simon, On Fri, 2013-01-25 at 13:35 +0900, Simon Horman wrote: > On Fri, Jan 25, 2013 at 01:15:03PM +0900, Simon Horman wrote: > > On Thu, Jan 24, 2013 at 07:00:32PM -0600, dinguyen@altera.com wrote: > > > From: Dinh Nguyen <dinguyen@altera.com> > > > > > > mach-socfpga is another platform that needs to use > > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > > > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > > > Cc: Arnd Bergmann <arnd@arndb.de> > > > Cc: Russell King <linux@arm.linux.org.uk> > > > Cc: Olof Johansson <olof@lixom.net> > > > Cc: Thomas Gleixner <tglx@linutronix.de> > > > Cc: Rob Herring <rob.herring@calxeda.com> > > > Cc: Sascha Hauer <kernel@pengutronix.de> > > > Cc: Simon Horman <horms@verge.net.au> > > > Cc: Magnus Damm <magnus.damm@gmail.com> > > > Cc: Stephen Warren <swarren@wwwdotorg.org> > > > Cc: Pavel Machek <pavel@denx.de> > > > > mach-shmobile portion: > > > > Acked-by: Simon Horman <horms+renesas@verge.net.au> > > For the record, I tested this on the kzm9g, kzm9d and marzen boards. Thanks, Dinh >
Hi Santosh, On Fri, 2013-01-25 at 13:43 +0530, Santosh Shilimkar wrote: > On Friday 25 January 2013 06:30 AM, dinguyen@altera.com wrote: > > From: Dinh Nguyen <dinguyen@altera.com> > > > > mach-socfpga is another platform that needs to use > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > > Cc: Arnd Bergmann <arnd@arndb.de> > > Cc: Russell King <linux@arm.linux.org.uk> > > Cc: Olof Johansson <olof@lixom.net> > > Cc: Thomas Gleixner <tglx@linutronix.de> > > Cc: Rob Herring <rob.herring@calxeda.com> > > Cc: Sascha Hauer <kernel@pengutronix.de> > > Cc: Simon Horman <horms@verge.net.au> > > Cc: Magnus Damm <magnus.damm@gmail.com> > > Cc: Stephen Warren <swarren@wwwdotorg.org> > > Cc: Pavel Machek <pavel@denx.de> > > --- > > arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- > > arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- > > arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- > > arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++++++++++++++ > > 4 files changed, 47 insertions(+), 138 deletions(-) > > > Does yor kernel skips the decompresser. Am just curious about > what you describe above since you should see the issue already > at decompresser. Your boot loader is expected to clean and > invalidating the caches before jumping into the kernel. This is for bringing up the 2nd core after the main CPU is already alive. Indeed, I did see this issue when the main CPU was coming up and have changed the bootloader to clean and invalidate the caches. Dinh > > Regards, > Santosh > >
Hi Pavel, On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote: > Hi! > > > mach-socfpga is another platform that needs to use > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > If there are three copies of code, with fourth one needed for next > platform, moving it into common code makes sense. > > But... The code was not identical before the merge. Are you sure that > the differences do not hurt? At the very least, it should be mentioned > in the changelog. Indeed, the addition of mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d This adds invalidate I-Cache as well as D-Cache, which I think should be ok for most platforms. Hopefully, Stephen can test and verify. Dinh > > Thanks, > Pavel > > > diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S > > index 7e49deb..921fc15 100644 > > --- a/arch/arm/mach-imx/headsmp.S > > +++ b/arch/arm/mach-imx/headsmp.S > > @@ -17,53 +17,6 @@ > > -ENTRY(v7_invalidate_l1) > > - mov r0, #0 > > - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache > > - mcr p15, 2, r0, c0, c0, 0 > > - mrc p15, 1, r0, c0, c0, 0 > ... > > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > > index 4a317fa..fb082c4 100644 > > --- a/arch/arm/mach-tegra/headsmp.S > > +++ b/arch/arm/mach-tegra/headsmp.S > > @@ -18,49 +18,6 @@ > > -ENTRY(v7_invalidate_l1) > > - mov r0, #0 > > - mcr p15, 2, r0, c0, c0, 0 > > - mrc p15, 1, r0, c0, c0, 0 > > [Note missing mcr p15, 0, .. line.] > >
On Friday 25 January 2013 09:50 PM, Dinh Nguyen wrote: > Hi Santosh, > > On Fri, 2013-01-25 at 13:43 +0530, Santosh Shilimkar wrote: >> On Friday 25 January 2013 06:30 AM, dinguyen@altera.com wrote: >>> From: Dinh Nguyen <dinguyen@altera.com> >>> >>> mach-socfpga is another platform that needs to use >>> v7_invalidate_l1 to bringup additional cores. There was a comment that >>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S >>> >>> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> >>> Cc: Arnd Bergmann <arnd@arndb.de> >>> Cc: Russell King <linux@arm.linux.org.uk> >>> Cc: Olof Johansson <olof@lixom.net> >>> Cc: Thomas Gleixner <tglx@linutronix.de> >>> Cc: Rob Herring <rob.herring@calxeda.com> >>> Cc: Sascha Hauer <kernel@pengutronix.de> >>> Cc: Simon Horman <horms@verge.net.au> >>> Cc: Magnus Damm <magnus.damm@gmail.com> >>> Cc: Stephen Warren <swarren@wwwdotorg.org> >>> Cc: Pavel Machek <pavel@denx.de> >>> --- >>> arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- >>> arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- >>> arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- >>> arch/arm/mm/cache-v7.S | 47 +++++++++++++++++++++++++++++++++++++ >>> 4 files changed, 47 insertions(+), 138 deletions(-) >>> >> Does yor kernel skips the decompresser. Am just curious about >> what you describe above since you should see the issue already >> at decompresser. Your boot loader is expected to clean and >> invalidating the caches before jumping into the kernel. > > This is for bringing up the 2nd core after the main CPU is already > alive. Indeed, I did see this issue when the main CPU was coming up and > have changed the bootloader to clean and invalidate the caches. > Ahh. I understand it now. Regards Santosh
On Fri 2013-01-25 10:24:17, Dinh Nguyen wrote: > Hi Pavel, > On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote: > > Hi! > > > > > mach-socfpga is another platform that needs to use > > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > > If there are three copies of code, with fourth one needed for next > > platform, moving it into common code makes sense. > > > > But... The code was not identical before the merge. Are you sure that > > the differences do not hurt? At the very least, it should be mentioned > > in the changelog. > > Indeed, the addition of > > mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache > > was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d > > This adds invalidate I-Cache as well as D-Cache, which I think should be > ok for most platforms. > > Hopefully, Stephen can test and verify. Otherwise it works for me... and looks like a good idea. Tested-by: Pavel Machek <pavel@denx.de> Reviewed-by: Pavel Machek <pavel@denx.de> Thanks, Pavel
On Thu 2013-01-24 20:42:08, Stephen Warren wrote: > On 01/24/2013 05:00 PM, dinguyen@altera.com wrote: > > From: Dinh Nguyen <dinguyen@altera.com> > > > > mach-socfpga is another platform that needs to use > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > > > -ENTRY(v7_invalidate_l1) > > - mov r0, #0 > > Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that > function from headsmp.S to reset-handler.S, so this patch will conflict. > How do you want to handle that? Drop the patch from Tegra tree and merge this one there? Having three copies of code is not nice to start with, no matter where it is... Pavel
On Fri, Jan 25, 2013 at 10:24:17AM -0600, Dinh Nguyen wrote: > Hi Pavel, > On Fri, 2013-01-25 at 16:49 +0100, Pavel Machek wrote: > > Hi! > > > > > mach-socfpga is another platform that needs to use > > > v7_invalidate_l1 to bringup additional cores. There was a comment that > > > the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > > > > If there are three copies of code, with fourth one needed for next > > platform, moving it into common code makes sense. > > > > But... The code was not identical before the merge. Are you sure that > > the differences do not hurt? At the very least, it should be mentioned > > in the changelog. > > Indeed, the addition of > > mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache > This becomes unnecessary since commit 612539e (ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards) gets in. Shawn > was done by commit # 5b2acf384c8a8707d32a98106192ee7187e4446d > > This adds invalidate I-Cache as well as D-Cache, which I think should be > ok for most platforms. >
On 01/28/2013 03:45 AM, Pavel Machek wrote: > On Thu 2013-01-24 20:42:08, Stephen Warren wrote: >> On 01/24/2013 05:00 PM, dinguyen@altera.com wrote: >>> From: Dinh Nguyen <dinguyen@altera.com> >>> >>> mach-socfpga is another platform that needs to use >>> v7_invalidate_l1 to bringup additional cores. There was a comment that >>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S >> >>> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S >> >>> -ENTRY(v7_invalidate_l1) >>> - mov r0, #0 >> >> Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that >> function from headsmp.S to reset-handler.S, so this patch will conflict. >> How do you want to handle that? > > Drop the patch from Tegra tree and merge this one there? Having three > copies of code is not nice to start with, no matter where it is... Well, I guess for other reasons rebasing the Tegra tree is useful for a few dependencies, so I'll drop that part of the patch which moves v7_invalidate_l1() from one file to another, so there shouldn't be any conflicts, and you can feel free to take this series through whatever tree you want. I haven't tested this patch yet though, to see whether the slight differences in the code in your patch mentioned in the other sub-thread affect Tegra at all. Hopefully I can test this later today.
Hi Stephen, On Mon, 2013-01-28 at 10:27 -0700, Stephen Warren wrote: > On 01/28/2013 03:45 AM, Pavel Machek wrote: > > On Thu 2013-01-24 20:42:08, Stephen Warren wrote: > >> On 01/24/2013 05:00 PM, dinguyen@altera.com wrote: > >>> From: Dinh Nguyen <dinguyen@altera.com> > >>> > >>> mach-socfpga is another platform that needs to use > >>> v7_invalidate_l1 to bringup additional cores. There was a comment that > >>> the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S > >> > >>> diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S > >> > >>> -ENTRY(v7_invalidate_l1) > >>> - mov r0, #0 > >> > >> Unfortunately, there's a patch in the Tegra tree for 3.9 that moves that > >> function from headsmp.S to reset-handler.S, so this patch will conflict. > >> How do you want to handle that? > > > > Drop the patch from Tegra tree and merge this one there? Having three > > copies of code is not nice to start with, no matter where it is... > > Well, I guess for other reasons rebasing the Tegra tree is useful for a > few dependencies, so I'll drop that part of the patch which moves > v7_invalidate_l1() from one file to another, so there shouldn't be any > conflicts, and you can feel free to take this series through whatever > tree you want. > > I haven't tested this patch yet though, to see whether the slight > differences in the code in your patch mentioned in the other sub-thread > affect Tegra at all. Hopefully I can test this later today. Shawn Guo mentioned that the instruction to invalidate I-Cache is unnecessary becauce of this commit: 612539e (ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards) So I'll send v2 without the extra instruction. Thanks, Dinh >
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb..921fc15 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -17,53 +17,6 @@ .section ".text.head", "ax" -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - #ifdef CONFIG_SMP ENTRY(v7_secondary_startup) bl v7_invalidate_l1 diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index b202c12..96001fd 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,54 +16,6 @@ __CPUINIT -/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! - * - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(shmobile_invalidate_start) bl v7_invalidate_l1 b secondary_startup diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4a317fa..fb082c4 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -18,49 +18,6 @@ .section ".text.head", "ax" __CPUINIT -/* - * Tegra specific entry point for secondary CPUs. - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(tegra_secondary_startup) bl v7_invalidate_l1 diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7539ec2..a7f7893 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -19,6 +19,53 @@ #include "proc-macros.S" /* + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +/* * v7_flush_icache_all() * * Flush the whole I-cache.