[i386] : btver2 pipeline descriptions.

Message ID	7794A52CE4D579448B959EED7DD0A47214F6D8D7@sausexdag05.amd.com
State	New
Headers	show Return-Path: <gcc-patches-return-335654-incoming=patchwork.ozlabs.org@gcc.gnu.org> Comment: DKIM? See http://www.dkim.org Comment: DomainKeys? See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:X-Forefront-Antispam-Report:X-SpamScore:X-BigFish:Received:Received:Received:X-M-MSG:Received:Received:Received:From:To:CC:Subject:Date:Message-ID:Content-Type:MIME-Version:X-OriginatorOrg:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=Uo1/9NRibrMJ3jXxHNSrw4I0yVhJNVRW9LVFqJEVbs3LutJHRblJ0U6YWZX49H j+5XI7JqZZ1drjoWN4bc1LcgXtGDPvdQqbwsxTmUUSWzRVQLsbomb4CBIa07iUIu sp2VVrUXX4ifutmnO0AV/piBYy0tdODzJQg9Y8/wGbYQM=; From: "Kumar, Venkataramanan" <Venkataramanan.Kumar@amd.com> To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org> CC: "Uros Bizjak (ubizjak@gmail.com)" <ubizjak@gmail.com> Subject: [Patch i386]: btver2 pipeline descriptions. Date: Thu, 17 Jan 2013 07:17:10 +0000 Message-ID: <7794A52CE4D579448B959EED7DD0A47214F6D8D7@sausexdag05.amd.com> Content-Type: multipart/mixed; boundary="_002_7794A52CE4D579448B959EED7DD0A47214F6D8D7sausexdag05amdc_" MIME-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org

Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 194705) +++ gcc/config/i386/i386.md (working copy) @@ -947,6 +947,7 @@ (include "athlon.md") (include "bdver1.md") (include "bdver3.md") +(include "btver2.md") (include "geode.md") (include "atom.md") (include "core2.md") @@ -5060,6 +5061,7 @@ (set_attr "athlon_decode" "double,direct") (set_attr "amdfam10_decode" "vector,double") (set_attr "bdver1_decode" "double,direct") + (set_attr "btver2_decode" "double,double") (set_attr "fp_int_src" "true")]) (define_insn "*float<SWI48:mode><MODEF:mode>2_sse_interunit" @@ -5081,6 +5083,7 @@ (set_attr "athlon_decode" "double,direct") (set_attr "amdfam10_decode" "vector,double") (set_attr "bdver1_decode" "double,direct") + (set_attr "btver2_decode" "double,double") (set_attr "fp_int_src" "true")]) (define_split @@ -11981,6 +11984,7 @@ [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") (set_attr "prefix_rep" "1") + (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) (define_insn "*bsf<mode>_1" @@ -11993,6 +11997,7 @@ "bsf{<imodesuffix>}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) (define_insn "ctz<mode>2" @@ -12054,26 +12059,28 @@ ;; BMI instructions. (define_insn "*bmi_andn_<mode>" - [(set (match_operand:SWI48 0 "register_operand" "=r") + [(set (match_operand:SWI48 0 "register_operand" "=r,r") (and:SWI48 (not:SWI48 - (match_operand:SWI48 1 "register_operand" "r")) - (match_operand:SWI48 2 "nonimmediate_operand" "rm"))) + (match_operand:SWI48 1 "register_operand" "r,r")) + (match_operand:SWI48 2 "nonimmediate_operand" "r,m"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI" "andn\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "bitmanip") + [(set_attr "type" "bitmanip,bitmanip") + (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) (define_insn "bmi_bextr_<mode>" - [(set (match_operand:SWI48 0 "register_operand" "=r") - (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") - (match_operand:SWI48 2 "nonimmediate_operand" "rm")] + [(set (match_operand:SWI48 0 "register_operand" "=r,r") + (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r,r") + (match_operand:SWI48 2 "nonimmediate_operand" "r,m")] UNSPEC_BEXTR)) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI" "bextr\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "bitmanip") + [(set_attr "type" "bitmanip,bitmanip") + (set_attr "btver2_decode" "direct, double") (set_attr "mode" "<MODE>")]) (define_insn "*bmi_blsi_<mode>" @@ -12086,6 +12093,7 @@ "TARGET_BMI" "blsi\t{%1, %0|%0, %1}" [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) (define_insn "*bmi_blsmsk_<mode>" @@ -12099,6 +12107,7 @@ "TARGET_BMI" "blsmsk\t{%1, %0|%0, %1}" [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) (define_insn "*bmi_blsr_<mode>" @@ -12112,6 +12121,7 @@ "TARGET_BMI" "blsr\t{%1, %0|%0, %1}" [(set_attr "type" "bitmanip") + (set_attr "btver2_decode" "double") (set_attr "mode" "<MODE>")]) ;; BMI2 instructions. @@ -13045,6 +13055,7 @@ "%vrcpss\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") + (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "maybe_vex") (set_attr "mode" "SF")]) @@ -13391,6 +13402,7 @@ "%vrsqrtss\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") + (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "maybe_vex") (set_attr "mode" "SF")]) @@ -13412,6 +13424,7 @@ "%vsqrt<ssemodesuffix>\t{%1, %d0|%d0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") + (set_attr "btver2_sse_attr" "sqrt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>") (set_attr "athlon_decode" "*") Index: gcc/config/i386/btver2.md =================================================================== --- gcc/config/i386/btver2.md (revision 0) +++ gcc/config/i386/btver2.md (revision 0) @@ -0,0 +1,1391 @@ +;; Copyright (C) 2012, Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; AMD btver2 scheduling + +;; Instructions decoded are that are classifed as direct (fast path single), +;; double (fast path double) and vector instructions. +;; Direct instrucions are decoded and convereted into 1 cop +;; Double instrucions are decoded and converetd into 2 cops +;; Vector instrucions are microcoded and they generated converted to +;; 3 or more cops. + +(define_attr "btver2_decode" "direct,vector,double" + (const_string "direct")) + +(define_attr "btver2_sse_attr" "other,rcp,sqrt,maxmin" + (const_string "other")) + +(define_automaton "btver2,btver2_int,btver2_agu,btver2_fp") + +;; Decoder decodes up to two insns (2 fastpath singles) or +;;(2 fastpath doubles) or combination of both at a cycle. +;; In case of vector (microded) instruction decoder decodes only one insn +;; at a cycle .To model that we have 2 "decoder" units. + +(define_cpu_unit "btver2-decode0" "btver2") +(define_cpu_unit "btver2-decode1" "btver2") + +;; "me" unit converts the decoded insn into cops. +;; It can generate upto 2 cops from two fast path singles in cycle x+1, +;; to model we have two "mes". In case of fast path double it converts +;; them to 2 cops in cycle x+1. Vector instructions are modelled to block +;; all decoder units. + +(define_cpu_unit "me0" "btver2") +(define_cpu_unit "me1" "btver2") + +(define_reservation "btver2-direct" "(btver2-decode0|btver2-decode1),(me0|me1)") + +(define_reservation "btver2-double" "(btver2-decode0|btver2-decode1),(me0+me1)") + +(define_reservation "btver2-vector" "(btver2-decode0+btver2-decode1),(me0+me1)") + +;; Integer operations +;; There are 2 ALU pipes + +(define_cpu_unit "btver2-ieu0" "btver2_int") +(define_cpu_unit "btver2-ieu1" "btver2_int") + +;; There are 2 AGU pipes one for load and one for store. + +(define_cpu_unit "btver2-load" "btver2_agu") +(define_cpu_unit "btver2-store" "btver2_agu") + +;; ALU operations can take place in ALU pipe0 or pipe1. +(define_reservation "btver2-alu" "(btver2-ieu0|btver2-ieu1)") + +;; MUL and DIV operations can take place in to ALU pipe1. +(define_reservation "btver2-mul" "btver2-ieu1") +(define_reservation "btver2-div" "btver2-ieu1") + +;; vectorpath (microcoded) instructions are single issue instructions. +;; So, they occupy all the integer units. +(define_reservation "btver2-ivector" "btver2-ieu0+btver2-ieu1+ + btver2-load+btver2-store") + +;;Floating point pipes. +(define_cpu_unit "btver2-fp0" "btver2_fp") +(define_cpu_unit "btver2-fp1" "btver2_fp") + +(define_reservation "btver2-fpa" "btver2-fp0") +(define_reservation "btver2-vimul" "btver2-fp0") +(define_reservation "btver2-valu" "btver2-fp0|btver2-fp1") +(define_reservation "btver2-stc" "btver2-fp1") +(define_reservation "btver2-fpm" "btver2-fp1") + +;; vectorpath (microcoded) instructions are single issue instructions. +;; So, they occupy all the fp units. +(define_reservation "btver2-fvector" "btver2-fp0+btver2-fp1+ + btver2-load+btver2-store") + +;; Call instruction +(define_insn_reservation "btver2_call" 2 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "call,callv")) + "btver2-double,btver2-load") + +;; General instructions +;; + +(define_insn_reservation "btver2_push_mem" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (eq_attr "type" "push"))) + "btver2-direct,btver2-load,btver2-alu") + +(define_insn_reservation "btver2_push" 1 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "push")) + "btver2-direct,btver2-alu") + +(define_insn_reservation "btver2_pop_mem" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (eq_attr "type" "pop"))) + "btver2-direct,btver2-load,btver2-alu") + +(define_insn_reservation "btver2_pop" 1 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "pop")) + "btver2-direct,btver2-alu") + +(define_insn_reservation "btver2_leave" 3 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "leave")) + "btver2-double,btver2-alu") + +(define_insn_reservation "btver2_lea" 1 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "lea")) + "btver2-direct,btver2-alu") + +;; Integer +(define_insn_reservation "btver2_imul_DI" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "DI") + (eq_attr "memory" "none,unknown")))) + "btver2-direct,btver2-mul*4") + +(define_insn_reservation "btver2_imul" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imul") + (eq_attr "memory" "none,unknown"))) + "btver2-direct,btver2-mul") + +(define_insn_reservation "btver2_imul_mem_DI" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imul") + (and (eq_attr "mode" "DI") + (eq_attr "memory" "load,both")))) + "btver2-direct,btver2-load,btver2-mul*4") + +(define_insn_reservation "btver2_imul_mem" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imul") + (eq_attr "memory" "load,both"))) + "btver2-direct,btver2-load,btver2-mul") + +(define_insn_reservation "btver2_idiv_DI" 41 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "DI") + (eq_attr "memory" "none,unknown")))) + "btver2-double,btver2-div") + +(define_insn_reservation "btver2_idiv_mem_DI" 44 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "DI") + (eq_attr "memory" "load")))) + "btver2-double,btver2-load,btver2-div") + +(define_insn_reservation "btver2_idiv_SI" 25 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") + (eq_attr "memory" "none,unknown")))) + "btver2-double,btver2-div*25") + +(define_insn_reservation "btver2_idiv_mem_SI" 28 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") + (eq_attr "memory" "load")))) + "btver2-double,btver2-load,btver2-div*25") + +(define_insn_reservation "btver2_idiv_HI" 17 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "HI") + (eq_attr "memory" "none,unknown")))) + "btver2-double,btver2-div*17") + +(define_insn_reservation "btver2_idiv_mem_HI" 20 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "HI") + (eq_attr "memory" "load")))) + "btver2-double,btver2-load,btver2-div*17") + +(define_insn_reservation "btver2_idiv_QI" 12 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") + (eq_attr "memory" "none,unknown")))) + "btver2-direct,btver2-div*12") + +(define_insn_reservation "btver2_idiv_mem_QI" 15 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "SI") + (eq_attr "memory" "load")))) + "btver2-direct,btver2-load,btver2-div*12") + +(define_insn_reservation "btver2_str" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "str") + (eq_attr "memory" "load,both,store"))) + "btver2-vector,btver2-ivector") + +(define_insn_reservation "btver2_idirect_loadmov" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imov") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,btver2-alu") + +(define_insn_reservation "btver2_idirect_load" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "bdver1_decode" "direct") + (and (eq_attr "unit" "integer,unknown") + (eq_attr "memory" "load")))) + "btver2-direct,btver2-load,btver2-alu") + +(define_insn_reservation "btver2_idirect_movstore" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "imov") + (eq_attr "memory" "store"))) + "btver2-direct,btver2-alu,btver2-store") + +(define_insn_reservation "btver2_idirect_both" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "bdver1_decode" "direct") + (and (eq_attr "unit" "integer,unknown") + (eq_attr "memory" "both")))) + "btver2-direct,btver2-load,btver2-alu,btver2-store") + +(define_insn_reservation "btver2_idirect_store" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "bdver1_decode" "direct") + (and (eq_attr "unit" "integer,unknown") + (eq_attr "memory" "store")))) + "btver2-direct,btver2-alu,btver2-store") + +;; Other integer instrucions +(define_insn_reservation "btver2_idirect" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "btver2_decode" "direct") + (and (eq_attr "unit" "integer,unknown") + (eq_attr "memory" "none,unknown")))) + "btver2-direct,btver2-alu") + +;; Floating point instructions +(define_insn_reservation "btver2_fldxf" 19 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fmov") + (and (eq_attr "memory" "load") + (eq_attr "mode" "XF")))) + "btver2-vector,btver2-load,btver2-fvector*5") + +(define_insn_reservation "btver2_fld" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,(btver2-fp0|btver2-fp1)") + +(define_insn_reservation "btver2_fstxf" 24 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fmov") + (and (eq_attr "memory" "both") + (eq_attr "mode" "XF")))) + "btver2-vector,btver2-fvector*9,btver2-store") + +(define_insn_reservation "btver2_fst" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "store,both"))) + "btver2-direct,btver2-fp1,btver2-store") + +(define_insn_reservation "btver2_fist" 9 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fistp,fisttp")) + "btver2-direct,btver2-load,btver2-fp1") + +(define_insn_reservation "btver2_fmov" 2 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fmov")) + "btver2-direct,(btver2-fp0|btver2-fp1)") + +(define_insn_reservation "btver2_fadd_load" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fop") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,btver2-fp0") + +(define_insn_reservation "btver2_fadd" 3 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fop")) + "btver2-direct,btver2-fp0") + +(define_insn_reservation "btver2_fmul_load" 10 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fmul") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,btver2-fp1*3") + +(define_insn_reservation "btver2_fmul" 5 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fmul")) + "btver2-direct,(btver2-fp1*3)") + +(define_insn_reservation "btver2_fsgn" 2 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fsgn")) + "btver2-direct,btver2-fp1*2") + +(define_insn_reservation "btver2_fdiv_load" 24 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fdiv") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,btver2-fp1*19") + +(define_insn_reservation "btver2_fdiv" 19 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fdiv")) + "btver2-direct,btver2-fp1*19") + +(define_insn_reservation "btver2_fcmov_load" 12 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fcmov") + (eq_attr "memory" "load"))) + "btver2-vector,btver2-load,(btver2-fp0|btver2-fp1)*7") + +(define_insn_reservation "btver2_fcmov" 7 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fcmov")) + "btver2-vector,(btver2-fp0|btver2-fp1)*7") + +(define_insn_reservation "btver2_fcomi_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fcmp") + (and (eq_attr "bdver1_decode" "double") + (eq_attr "memory" "load")))) + "btver2-direct,btver2-load,btver2-fp0*2") + +(define_insn_reservation "btver2_fcomi" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "bdver1_decode" "double") + (eq_attr "type" "fcmp"))) + "btver2-direct, btver2-fp0*2") + +(define_insn_reservation "btver2_fcom_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "type" "fcmp") + (eq_attr "memory" "load"))) + "btver2-direct,btver2-load,btver2-fp0") + +(define_insn_reservation "btver2_fcom" 1 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fcmp")) + "btver2-direct,btver2-fp0") + +(define_insn_reservation "btver2_fxch" 1 + (and (eq_attr "cpu" "btver2") + (eq_attr "type" "fxch")) + "btver2-direct,btver2-fp1") + +;; SSE AVX maxmin,rcp,sqrt +(define_insn_reservation "btver2_sse_maxmin" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4DF,V2DF,V4SF,SF,DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "maxmin") + (eq_attr "type" "sse,sseadd"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_sse_maxmin_mem" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4DF,V2DF,V4SF,SF,DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "maxmin") + (eq_attr "type" "sse,sseadd"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_sse_rcp" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF,SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "rcp") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-fpm") + +(define_insn_reservation "btver2_sse_rcp_mem" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF,SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "rcp") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-load,btver2-fpm") + +(define_insn_reservation "btver2_avx_rcp" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "rcp") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-fpm*2") + +(define_insn_reservation "btver2_avx_rcp_mem" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "rcp") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-load,btver2-fpm*2") + +(define_insn_reservation "btver2_sse_sqrt_v4sf" 21 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-fpm*21") + +(define_insn_reservation "btver2_sse_sqrt_v4sf_mem" 26 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-load,btver2-fpm*21") + +(define_insn_reservation "btver2_sse_sqrt_v4df" 54 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-fpm*54") + +(define_insn_reservation "btver2_sse_sqrt_v4df_mem" 59 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-load,btver2-fpm*54") + +(define_insn_reservation "btver2_sse_sqrt_sf" 16 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-fpm*16") + +(define_insn_reservation "btver2_sse_sqrt_sf_mem" 21 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-load,btver2-fpm*16") + +(define_insn_reservation "btver2_sse_sqrt_df" 27 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-fpm*27") + +(define_insn_reservation "btver2_sse_sqrt_df_mem" 32 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-direct,btver2-load,btver2-fpm*27") + +(define_insn_reservation "btver2_sse_sqrt_v8sf" 42 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-fpm*42") + +(define_insn_reservation "btver2_sse_sqrt_v8sf_mem" 42 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_sse_attr" "sqrt") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-load,btver2-fpm*42") + +;; Bitmanipulation instrucions BMI LZCNT POPCNT +(define_insn_reservation "btver2_bmi_reg_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "btver2_decode" "direct") + (and (eq_attr "memory" "none") + (eq_attr "type" "bitmanip")))) + "btver2-direct,btver2-alu") + +(define_insn_reservation "btver2_bmi_mem_direct" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "btver2_decode" "direct") + (and (eq_attr "memory" "load") + (eq_attr "type" "bitmanip")))) + "btver2-direct,btver2-load,btver2-alu") + +(define_insn_reservation "btver2_bmi_reg_double" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "btver2_decode" "double") + (and (eq_attr "memory" "none") + (eq_attr "type" "bitmanip,alu1")))) + "btver2-double,btver2-alu") + +(define_insn_reservation "btver2_bmi_double_store" 5 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "store") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "bitmanip,alu1")))) + "btver2-double,btver2-alu,btver2-store") + +(define_insn_reservation "btver2_bmi_double_load" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "btver2_decode" "double") + (and (eq_attr "memory" "load") + (eq_attr "type" "bitmanip,alu1")))) + "btver2-double,btver2-load,btver2-alu") + +;; F16C converts +(define_insn_reservation "btver2_ssecvt_load_direct" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecvt"))))) + "btver2-direct,btver2-load,btver2-stc") + +(define_insn_reservation "btver2_ssecvt_store_direct" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "memory" "store") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecvt"))))) + "btver2-direct,btver2-stc,btver2-store") + +(define_insn_reservation "btver2_ssecvt_reg_direct" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecvt")))) + "btver2-direct,btver2-stc") + +(define_insn_reservation "btver2_ssecvt_load_double" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt"))))) + "btver2-double,btver2-load,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_reg_double" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt")))) + "btver2-double,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_store_vector" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "memory" "store") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssecvt"))))) + "btver2-vector,btver2-stc,(btver2-fpa|btver2-fpm),btver2-store") + +(define_insn_reservation "btver2_ssecvt_reg_vector" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4SF") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssecvt")))) + "btver2-vector,btver2-stc,(btver2-fpa|btver2-fpm)") + +;; avx256 adds +(define_insn_reservation "btver2_avx_add_load_256" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "sseadd,sseadd1")))) + "btver2-double,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_avx_add_reg_256" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "sseadd,sseadd1")))) + "btver2-double,btver2-fpa") + +;; avx256 logs +(define_insn_reservation "btver2_avx_load_log" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "sselog,sselog1"))))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_avx_reg_log" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "sselog,sselog1"))))) + "btver2-double,(btver2-fpa|btver2-fpm)") + +;; avx256 sse + +(define_insn_reservation "btver2_avx_load_sse" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "sse"))))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_avx_reg_sse" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "sse"))))) + "btver2-double,(btver2-fpa|btver2-fpm)") + +;; avx256 moves +(define_insn_reservation "btver2_avx_load_int_mov" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "OI") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssemov")))) + "btver2-double,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_avx_store_int_mov" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "OI") + (and (eq_attr "memory" "store") + (eq_attr "type" "ssemov")))) + "btver2-double,btver2-valu,btver2-store") + +(define_insn_reservation "btver2_avx_int_mov" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "OI") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssemov")))) + "btver2-double,btver2-valu") + +(define_insn_reservation "btver2_avx_load_from_vectors" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4DF") + (and (ior ( match_operand:V4SF 1 "memory_operand") + ( match_operand:V2DF 1 "memory_operand")) + (and (eq_attr "memory" "load") + (eq_attr "type" "ssemov"))))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_avx_loads_from_scalar" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF,V4DF") + (and (ior ( match_operand:SF 1 "memory_operand") + ( match_operand:DF 1 "memory_operand")) + (and (eq_attr "memory" "load") + (eq_attr "type" "ssemov"))))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)*2") + +(define_insn_reservation "btver2_avx_store_move" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "store") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemov"))))) + "btver2-double,(btver2-fpa|btver2-fpm),btver2-store") + +(define_insn_reservation "btver2_avx_load_move" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemov"))))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_avx_reg_move" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemov"))))) + "btver2-double,(btver2-fpa|btver2-fpm)") +;; avx256 cmps +(define_insn_reservation "btver2_avx_load_cmp" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssecmp")))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)*2") + +(define_insn_reservation "btver2_avx_cmp" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssecmp")))) + "btver2-double,(btver2-fpa|btver2-fpm)*2") + +;; ssecvts 256 +(define_insn_reservation "btver2_ssecvt_256_load" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,OI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssecvt"))))) + "btver2-double,btver2-load,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_256" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,OI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssecvt"))))) + "btver2-double,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_256_vector_load" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,OI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssecvt"))))) + "btver2-vector,btver2-load,btver2-stc*2,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_ssecvt_256_vector" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,OI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssecvt"))))) + "btver2-vector,btver2-stc*2,(btver2-fpa|btver2-fpm)") + +;; avx256 divides +(define_insn_reservation "btver2_avx_load_div" 43 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssediv"))))) + "btver2-double,btver2-load,btver2-fpm*38") + +(define_insn_reservation "btver2_avx_div" 38 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF,V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssediv"))))) + "btver2-double,btver2-fpm*38") + +;; avx256 multiply + +(define_insn_reservation "btver2_avx_mul_load_pd" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemul"))))) + "btver2-double,btver2-load,btver2-fpm*4") + +(define_insn_reservation "btver2_avx_mul_load_ps" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemul"))))) + "btver2-double,btver2-load,btver2-fpm*2") + + +(define_insn_reservation "btver2_avx_mul_256_pd" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemul"))))) + "btver2-double,btver2-fpm*4") + +(define_insn_reservation "btver2_avx_mul_256_ps" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssemul"))))) + "btver2-double,btver2-fpm*2") + +(define_insn_reservation "btver2_avx_dpps_load_ps" 17 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-fpm*6,btver2-fpa*6") + +(define_insn_reservation "btver2_avx_dpps_ps" 12 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-fpm*6,btver2-fpa*6") + +;; AES/CLMUL + +(define_insn_reservation "btver2_aes_double" 3 + (and (eq_attr "cpu" "btver2") + (and (match_operand:V2DI 0 "register_operand") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "sselog1"))))) + "btver2-double,btver2-valu,btver2-vimul") + +(define_insn_reservation "btver2_aes_direct" 2 + (and (eq_attr "cpu" "btver2") + (and (match_operand:V2DI 0 "register_operand") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sselog1"))))) + "btver2-direct,btver2-vimul") + +;; AVX128 SSE4* SSSE3 SSE3* SSE2 SSE instructions + +(define_insn_reservation "btver2_sseint_load_direct" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sse,ssecmp,sseiadd"))))) + "btver2-direct,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_sseint_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sse,ssecmp,sseiadd"))))) + "btver2-direct,btver2-valu") + +(define_insn_reservation "btver2_sselog_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sse,sselog"))))) + "btver2-direct,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sselog_load_direct" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sse,sselog"))))) + "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_intext_reg_128" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF,QI,SI,HI,SI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sselog"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_sse_mov_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov"))))) + "btver2-direct,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_mov_vector" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemov"))))) + "btver2-vector,(btver2-fpa|btver2-fpm)*2") + +(define_insn_reservation "btver2_ssecomi_load_128" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssecomi"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_ssecomi_reg_128" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "!vector") + (eq_attr "type" "ssecomi"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_ssemul_load_v2df" 14 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-load,btver2-fpm*2,btver2-fpa") + +(define_insn_reservation "btver2_ssemul_reg_v2df" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-fpm*2,btver2-fpa") + +(define_insn_reservation "btver2_ssemul_load_v4sf" 16 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-load,btver2-fpm*3,btver2-fpa*2") + +(define_insn_reservation "btver2_ssemul_reg_v4sf" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemul"))))) + "btver2-vector,btver2-fpm*3,btver2-fpa*2") + +(define_insn_reservation "btver2_sse_store_vectmov" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemov")))) + "btver2-vector,btver2-valu*3,btver2-store") + +(define_insn_reservation "btver2_sse_load_vectmov" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemov")))) + "btver2-vector,btver2-load,btver2-valu*3") + +(define_insn_reservation "btver2_sse_vectmov" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "ssemov")))) + "btver2-vector,btver2-valu*3") + + +(define_insn_reservation "btver2_sseimul" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseimul")))) + "btver2-direct,btver2-vimul") + +(define_insn_reservation "btver2_sseimul_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseimul")))) + "btver2-direct,btver2-load,btver2-vimul") + +(define_insn_reservation "btver2_sseimul_load_vect" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "sseimul")))) + "btver2-vector,btver2-load,btver2-vimul*2,btver2-valu") + +(define_insn_reservation "btver2_sseimul_vect" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "sseimul")))) + "btver2-vector,btver2-vimul*2,btver2-valu") + +(define_insn_reservation "btver2_sseins" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "sseins"))) + "btver2-vector,btver2-valu*3") + +(define_insn_reservation "btver2_sseishft_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseishft")))) + "btver2-direct,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_sseishft_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseishft")))) + "btver2-direct,btver2-valu") + +(define_insn_reservation "btver2_sselog1_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "!V8SF,!V4DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sselog1"))))) + "btver2-direct,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_sselog1_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "!V8SF,!V4DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sselog1"))))) + "btver2-direct,btver2-valu") + +(define_insn_reservation "btver2_sselog1_vector_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "sselog1")))) + "btver2-vector,btver2-valu*2") + +(define_insn_reservation "btver2_sselog1_vector" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "vector") + (eq_attr "type" "sselog1")))) + "btver2-vector,btver2-valu*2") + +(define_insn_reservation "btver2_sseadd_load" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF,V2DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseadd,sseadd1"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_sseadd_reg" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V4SF,V2DF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseadd,sseadd1"))))) + "btver2-direct,btver2-fpa") + +;;SSE2 SSEint SSEfp SSE + +(define_insn_reservation "btver2_sseint_to_scalar_move_with_load" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI,DI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_sseint_to_scalar_move_with_store" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI,DI") + (and (eq_attr "memory" "store") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov"))))) + "btver2-direct,btver2-fpa,btver2-store") + + +(define_insn_reservation "btver2_scalar_to_sseint_move_with_load" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (ior ( match_operand:SI 1 "memory_operand") + ( match_operand:DI 1 "memory_operand")) + (eq_attr "type" "ssemov")))) + "btver2-direct,btver2-load,btver2-stc,btver2-valu") + +(define_insn_reservation "btver2_sseint_to_scalar" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI,DI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_scalar_to_sseint" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (ior ( match_operand:SI 1 "register_operand") + ( match_operand:DI 1 "register_operand")) + (eq_attr "type" "ssemov")))) + "btver2-direct,btver2-stc,btver2-valu") + +(define_insn_reservation "btver2_sse_int_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov,sselog,sseishft1"))))) + "btver2-direct,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_sse_int_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov,sselog,sseishft1"))))) + "btver2-direct,btver2-valu") + +(define_insn_reservation "btver2_sse_int_cvt_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseicvt"))))) + "btver2-direct,btver2-load,btver2-valu") + +(define_insn_reservation "btver2_sse_int_cvt" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseicvt"))))) + "btver2-direct,btver2-valu") + +(define_insn_reservation "btver2_sse_int_32_move" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI,DI") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_int_32_sse_move" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI") + (and (ior ( match_operand:SI 1 "register_operand") + ( match_operand:DI 1 "register_operand")) + (eq_attr "type" "ssemov")))) + "btver2-direct,btver2-stc,btver2-valu") + +(define_insn_reservation "btver2_sse2cvt_load_direct" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI,V4SF,V2DF,DI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecvt"))))) + "btver2-direct,btver2-load,btver2-stc") + +(define_insn_reservation "btver2_sse2cvt_reg_direct" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "TI,V4SF,V2DF,DI") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecvt")))) + "btver2-direct,btver2-stc") + +(define_insn_reservation "btver2_sseicvt_load_si" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "sseicvt"))))) + "btver2-double,btver2-load,btver2-stc,btver2-fpa") + +(define_insn_reservation "btver2_sseicvt_si" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SI") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "sseicvt")))) + "btver2-double,btver2-stc,btver2-fpa") + +(define_insn_reservation "btver2_ssecvt_load_df" 11 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt"))))) + "btver2-double,btver2-load,btver2-stc*2") + + +(define_insn_reservation "btver2_ssecvt_df" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt")))) + "btver2-double,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_load_sf" 12 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt"))))) + "btver2-double,btver2-load,btver2-stc*2") + +(define_insn_reservation "btver2_ssecvt_sf" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "ssecvt")))) + "btver2-double,btver2-stc*2") + +(define_insn_reservation "btver2_sseicvt_load_df" 14 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "sseicvt"))))) + "btver2-double,btver2-load,btver2-stc") +;;st,ld-stc +(define_insn_reservation "btver2_sseicvt_df" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "btver2_decode" "double") + (eq_attr "type" "sseicvt")))) + "btver2-double,btver2-stc") + + +(define_insn_reservation "btver2_scalar_sse_load_add" 8 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseadd"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_scalar_sse_add" 3 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "sseadd"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_int_sse_cmp_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF,DF,SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecmp"))))) + "btver2-direct,btver2-load,btver2-fpa") + +(define_insn_reservation "btver2_int_sse_cmp" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,V4SF,DF,SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecmp"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_int_sse_comsi_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecomi"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_int_sse_comsi" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "DF,SF") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssecomi"))))) + "btver2-direct,btver2-fpa") + +(define_insn_reservation "btver2_ssemmx_mov_load_default" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov,mmxmov")))) + "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_ssemmx_mov_store_default" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "store,both") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov,mmxmov")))) + "btver2-direct,(btver2-fpa|btver2-fpm),btver2-store") + +(define_insn_reservation "btver2_sse_mov_default" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "btver2_decode" "direct") + (eq_attr "type" "ssemov,mmxmov")))) + "btver2-direct,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_shuf_double" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "mode" "V4DF,V8SF") + (eq_attr "type" "sseshuf")))) + "btver2-double,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_shuf_direct" 1 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "none,unknown") + (and (eq_attr "mode" "V2DF,V4SF") + (eq_attr "type" "sseshuf,sseshuf1")))) + "btver2-direct,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_shuf_double_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "mode" "V4DF,V8SF") + (eq_attr "type" "sseshuf")))) + "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_shuf_direct_load" 6 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "memory" "load") + (and (eq_attr "mode" "V2DF,V4SF") + (eq_attr "type" "sseshuf,sseshuf1")))) + "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)") + +(define_insn_reservation "btver2_sse_div" 19 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssediv")))) + "btver2-direct,btver2-fpm*19") + +(define_insn_reservation "btver2_sse_div_sf" 14 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssediv")))) + "btver2-direct,btver2-fpm*14") + +(define_insn_reservation "btver2_sse_mul" 4 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF,SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssemul")))) + "btver2-direct,btver2-fpm*2") + +(define_insn_reservation "btver2_sse_mul_sf" 2 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF,SF") + (and (eq_attr "memory" "none,unknown") + (eq_attr "type" "ssemul")))) + "btver2-direct,btver2-fpm") + +(define_insn_reservation "btver2_sse_div_load" 24 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssediv")))) + "btver2-direct,btver2-load,btver2-fpm*19") + +(define_insn_reservation "btver2_sse_div_sf_load" 19 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssediv")))) + "btver2-direct,btver2-load,btver2-fpm*14") + +(define_insn_reservation "btver2_sse_mul_load" 9 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF,SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssemul")))) + "btver2-direct,btver2-load,btver2-fpm*2") + +(define_insn_reservation "btver2_sse_mul_sf_load" 7 + (and (eq_attr "cpu" "btver2") + (and (eq_attr "mode" "V2DF,DF,V4SF,SF") + (and (eq_attr "memory" "load") + (eq_attr "type" "ssemul")))) + "btver2-direct,btver2-load,btver2-fpm") + Index: gcc/config/i386/sse.md =================================================================== --- gcc/config/i386/sse.md (revision 194705) +++ gcc/config/i386/sse.md (working copy) @@ -899,6 +899,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "ssemul") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "direct,double") (set_attr "mode" "<MODE>")]) (define_insn "<sse>_vmmul<mode>3" @@ -973,6 +974,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "ssediv") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "direct,double") (set_attr "mode" "<ssescalarmode>")]) (define_insn "<sse>_rcp<mode>2" @@ -983,6 +985,7 @@ "%vrcpps\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") + (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) @@ -1000,6 +1003,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") (set_attr "atom_sse_attr" "rcp") + (set_attr "btver2_sse_attr" "rcp") (set_attr "prefix" "orig,vex") (set_attr "mode" "SF")]) @@ -1031,6 +1035,7 @@ "%vsqrt<ssemodesuffix>\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") + (set_attr "btver2_sse_attr" "sqrt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) @@ -1048,6 +1053,7 @@ [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") + (set_attr "btver2_sse_attr" "sqrt") (set_attr "prefix" "orig,vex") (set_attr "mode" "<ssescalarmode>")]) @@ -1115,6 +1121,7 @@ v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") + (set_attr "btver2_sse_attr" "maxmin") (set_attr "prefix" "orig,vex") (set_attr "mode" "<MODE>")]) @@ -1129,6 +1136,7 @@ v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") + (set_attr "btver2_sse_attr" "maxmin") (set_attr "prefix" "orig,vex") (set_attr "mode" "<MODE>")]) @@ -1146,6 +1154,7 @@ v<maxmin_float><ssescalarmodesuffix>\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sse") + (set_attr "btver2_sse_attr" "maxmin") (set_attr "prefix" "orig,vex") (set_attr "mode" "<ssescalarmode>")]) @@ -2418,6 +2427,7 @@ (set_attr "athlon_decode" "vector,double,*") (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "double,direct,*") + (set_attr "btver2_decode" "double,double,double") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "SF")]) @@ -2438,6 +2448,7 @@ (set_attr "athlon_decode" "vector,double,*") (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "double,direct,*") + (set_attr "btver2_decode" "double,double,double") (set_attr "length_vex" "*,*,4") (set_attr "prefix_rex" "1,1,*") (set_attr "prefix" "orig,orig,vex") @@ -2646,6 +2657,7 @@ [(set_attr "type" "ssecvt") (set_attr "unit" "mmx") (set_attr "bdver1_decode" "double") + (set_attr "btver2_decode" "direct") (set_attr "prefix_data16" "1") (set_attr "mode" "DI")]) @@ -2677,6 +2689,7 @@ (set_attr "athlon_decode" "double,direct,*") (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "double,direct,*") + (set_attr "btver2_decode" "double,double,double") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "DF")]) @@ -2714,6 +2727,7 @@ [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") + (set_attr "btver2_decode" "double,double") (set_attr "prefix_rep" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) @@ -2774,6 +2788,7 @@ (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") (set_attr "bdver1_decode" "double,double") + (set_attr "btver2_decode" "double,double") (set_attr "prefix_rep" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "SI")]) @@ -2857,6 +2872,7 @@ "vcvtpd2dq{y}\t{%1, %x0|%x0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) (define_expand "sse2_cvtpd2dq" @@ -2916,6 +2932,7 @@ "vcvttpd2dq{y}\t{%1, %x0|%x0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) (define_expand "sse2_cvttpd2dq" @@ -2963,6 +2980,7 @@ (set_attr "athlon_decode" "vector,double,*") (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "direct,direct,*") + (set_attr "btver2_decode" "double,double,double") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "SF")]) @@ -2985,6 +3003,7 @@ (set_attr "amdfam10_decode" "vector,double,*") (set_attr "athlon_decode" "direct,direct,*") (set_attr "bdver1_decode" "direct,direct,*") + (set_attr "btver2_decode" "double,double,double") (set_attr "prefix" "orig,orig,vex") (set_attr "mode" "DF")]) @@ -2996,6 +3015,7 @@ "vcvtpd2ps{y}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "V4SF")]) (define_expand "sse2_cvtpd2ps" @@ -5638,6 +5658,7 @@ (set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<sseinsnmode>")]) (define_expand "mul<mode>3" @@ -8277,6 +8298,7 @@ (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn "ssse3_pshufbv8qi3" @@ -8513,6 +8535,7 @@ (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<MODE>")]) (define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>" @@ -8532,6 +8555,7 @@ (set_attr "prefix_data16" "1,*") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<MODE>")]) (define_insn "<sse4_1_avx2>_movntdqa" @@ -8561,6 +8585,7 @@ (set_attr "length_immediate" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn "avx2_packusdw" @@ -8610,6 +8635,7 @@ (set_attr "prefix_extra" "1") (set_attr "length_immediate" "*,1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "vector,vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn "sse4_1_pblendw" @@ -8869,6 +8895,7 @@ [(set_attr "type" "ssecomi") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) (define_insn "sse4_1_ptest" @@ -9211,6 +9238,7 @@ (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "length_immediate" "1") + (set_attr "btver2_decode" "vector") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) @@ -9238,6 +9266,7 @@ (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") + (set_attr "btver2_decode" "vector") (set_attr "memory" "none,load") (set_attr "mode" "TI")]) @@ -9263,6 +9292,7 @@ (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") + (set_attr "btver2_decode" "vector,vector,vector,vector") (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) @@ -9391,6 +9421,7 @@ (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") + (set_attr "btver2_decode" "vector") (set_attr "mode" "TI")]) (define_insn "sse4_2_pcmpistrm" @@ -9414,6 +9445,7 @@ (set_attr "length_immediate" "1") (set_attr "prefix" "maybe_vex") (set_attr "memory" "none,load") + (set_attr "btver2_decode" "vector") (set_attr "mode" "TI")]) (define_insn "sse4_2_pcmpistr_cconly" @@ -9437,6 +9469,7 @@ (set_attr "length_immediate" "1") (set_attr "memory" "none,load,none,load") (set_attr "prefix" "maybe_vex") + (set_attr "btver2_decode" "vector,vector,vector,vector") (set_attr "mode" "TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -10299,6 +10332,7 @@ (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "double,double") (set_attr "mode" "TI")]) (define_insn "aesenclast" @@ -10314,6 +10348,7 @@ (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "double,double") (set_attr "mode" "TI")]) (define_insn "aesdec" @@ -10329,6 +10364,7 @@ (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "double,double") (set_attr "mode" "TI")]) (define_insn "aesdeclast" @@ -10344,6 +10380,7 @@ (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "orig,vex") + (set_attr "btver2_decode" "double,double") (set_attr "mode" "TI")]) (define_insn "aesimc" @@ -10416,6 +10453,7 @@ (set_attr "modrm" "0") (set_attr "memory" "none") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) ;; Clear the upper 128bits of AVX registers, equivalent to a NOP @@ -10428,6 +10466,7 @@ (set_attr "modrm" "0") (set_attr "memory" "none") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "OI")]) (define_mode_attr AVXTOSSEMODE @@ -10746,6 +10785,7 @@ [(set_attr "type" "sselog") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "<MODE>")]) (define_expand "avx_vperm2f128<mode>3" @@ -11033,6 +11073,7 @@ [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>" @@ -11047,6 +11088,7 @@ [(set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "<sseinsnmode>")]) (define_insn_and_split "avx_<castmode><avxsizesuffix>_<castmode>" @@ -11211,6 +11253,7 @@ "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "double") (set_attr "mode" "V8SF")]) (define_expand "vcvtps2ph" @@ -11256,6 +11299,7 @@ "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "vex") + (set_attr "btver2_decode" "vector") (set_attr "mode" "V8SF")]) ;; For gather* insn patterns Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 194705) +++ gcc/config/i386/i386.c (working copy) @@ -1745,10 +1745,10 @@ #define m_BDVER1 (1<<PROCESSOR_BDVER1) #define m_BDVER2 (1<<PROCESSOR_BDVER2) #define m_BDVER3 (1<<PROCESSOR_BDVER3) +#define m_BTVER1 (1<<PROCESSOR_BTVER1) +#define m_BTVER2 (1<<PROCESSOR_BTVER2) #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3) #define m_BTVER (m_BTVER1 | m_BTVER2) -#define m_BTVER1 (1<<PROCESSOR_BTVER1) -#define m_BTVER2 (1<<PROCESSOR_BTVER2) #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER) #define m_GENERIC32 (1<<PROCESSOR_GENERIC32) @@ -2994,7 +2994,7 @@ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE}, - {"btver2", PROCESSOR_BTVER2, CPU_GENERIC64, + {"btver2", PROCESSOR_BTVER2, CPU_BTVER2, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX

[i386] : btver2 pipeline descriptions.

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