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[U-Boot,V2,1/4] EXYNOS5: Change parent clock of FIMD to MPLL

Message ID 1355398167-24845-2-git-send-email-ajaykumar.rs@samsung.com
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Commit Message

Ajay Kumar Dec. 13, 2012, 11:29 a.m. UTC 
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/cpu/armv7/exynos/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Minkyu Kang Dec. 15, 2012, 5:13 a.m. UTC | #1 
Dear Donghwa,

On 13/12/12 20:29, Ajay Kumar wrote:
> With VPLL as source clock to FIMD,
> Exynos DP Initializaton was failing sometimes with unstable clock.
> Changing FIMD source to MPLL resolves this issue.
> 
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>  arch/arm/cpu/armv7/exynos/clock.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index fe61f88..bfcd5f7 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void)
>  	 */
>  	cfg = readl(&clk->src_disp1_0);
>  	cfg &= ~(0xf);
> -	cfg |= 0x8;
> +	cfg |= 0x6;

Please check it.

>  	writel(cfg, &clk->src_disp1_0);
>  
>  	/*
> 

Thanks.
Minkyu Kang.
Donghwa Lee Dec. 17, 2012, 1:12 a.m. UTC | #2 
On 2012년 12월 15일 14:13, Minkyu Kang wrote:
> Dear Donghwa,
>
> On 13/12/12 20:29, Ajay Kumar wrote:
>> With VPLL as source clock to FIMD,
>> Exynos DP Initializaton was failing sometimes with unstable clock.
>> Changing FIMD source to MPLL resolves this issue.
>>
>> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>>   arch/arm/cpu/armv7/exynos/clock.c |    2 +-
>>   1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
>> index fe61f88..bfcd5f7 100644
>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>> @@ -603,7 +603,7 @@ void exynos5_set_lcd_clk(void)
>>   	 */
>>   	cfg = readl(&clk->src_disp1_0);
>>   	cfg &= ~(0xf);
>> -	cfg |= 0x8;
>> +	cfg |= 0x6;
> Please check it.
In order to use the configured refresh rate as closely as possible, it 
is more proper value(MPLL: 0x6) than
using VPLL as source clock.

Thank you,
Donghwa Lee
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..bfcd5f7 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -603,7 +603,7 @@  void exynos5_set_lcd_clk(void)
 	 */
 	cfg = readl(&clk->src_disp1_0);
 	cfg &= ~(0xf);
-	cfg |= 0x8;
+	cfg |= 0x6;
 	writel(cfg, &clk->src_disp1_0);
 
 	/*