| Message ID | 20121116020552.GA48755@cs.nctu.edu.tw |
|---|---|
| State | New |
| Headers | show |
On Fri, Nov 16, 2012 at 10:05:52AM +0800, 陳韋任 (Wei-Ren Chen) wrote: > Hi all, > > I check MIPS microMIPS manual [1], and found the major opcode might be > wrong. I add a comment to explicitly indicate what manual I am refering > to, and according that manual I remove microMIPS32 major opcodes 0x1f. > As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order > MIPS ISA level or new revision of this microMIPS architecture. Quote > from Johnson, they are belong MIPS64 [2]. > > Please review, thanks. > > [1] http://www.mips.com/products/architectures/micromips/#specifications > > MIPS Architecture for Programmers Volume II-B: > The microMIPS32 Instruction Set (Revision 3.05) > > MD00582-2B-microMIPS-AFP-03.05.pdf > > [2] http://www.mips.com/products/architectures/mips64/ > > MIPS Architecture For Programmers > Volume II-A: The MIPS64 Instruction Set > > MD00087-2B-MIPS64BIS-AFP-03.51.pdf > > Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> > --- > target-mips/translate.c | 24 +++++++++++++++++------- > 1 files changed, 17 insertions(+), 7 deletions(-) Please send this through Aurelian as maintainer for target-mips/. The discussion on previous the thread show this isn't qemu-trivial material :). Stefan
> Please send this through Aurelian as maintainer for target-mips/. The > discussion on previous the thread show this isn't qemu-trivial material > :). O.K., I'll remove this from qemu-trivial if I need to send revision next time. Thanks, Stefan. Regards, chenwj
Hi Chen, Again the format is incorrect. Please review the "SubmittingPatches 1.12" link on the http://wiki.qemu.org/Contribute/SubmitAPatch page. -Eric > -----Original Message----- > From: 陳韋任 (Wei-Ren Chen) [mailto:chenwj@iis.sinica.edu.tw] > Sent: Thursday, November 15, 2012 6:06 PM > To: qemu-devel@nongnu.org; qemu-trivial@nongnu.org > Cc: Johnson, Eric; Jia Liu; Aurelien Jarno > Subject: [PATCH v2] target-mips: Clean up microMIPS32 major opcode > > Hi all, > > I check MIPS microMIPS manual [1], and found the major opcode might be > wrong. I add a comment to explicitly indicate what manual I am refering > to, and according that manual I remove microMIPS32 major opcodes 0x1f. > As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order > MIPS ISA level or new revision of this microMIPS architecture. Quote > from Johnson, they are belong MIPS64 [2]. > > Please review, thanks. > > [1] http://www.mips.com/products/architectures/micromips/#specifications > > MIPS Architecture for Programmers Volume II-B: > The microMIPS32 Instruction Set (Revision 3.05) > > MD00582-2B-microMIPS-AFP-03.05.pdf > > [2] http://www.mips.com/products/architectures/mips64/ > > MIPS Architecture For Programmers > Volume II-A: The MIPS64 Instruction Set > > MD00087-2B-MIPS64BIS-AFP-03.51.pdf > > Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> > --- > target-mips/translate.c | 24 +++++++++++++++++------- > 1 files changed, 17 insertions(+), 7 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 01b48fa..1c0ff65 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env, > DisasContext *ctx, > return n_bytes; > } > > -/* microMIPS extension to MIPS32 */ > +/* microMIPS extension to MIPS32/MIPS64 */ > > -/* microMIPS32 major opcodes */ > +/* > + * microMIPS32/microMIPS64 major opcodes > + * > + * 1. MIPS Architecture for Programmers Volume II-B: > + * The microMIPS32 Instruction Set (Revision 3.05) > + * > + * Table 6.2 microMIPS32 Encoding of Major Opcode Field > + * > + * 2. MIPS Architecture For Programmers Volume II-A: > + * The MIPS64 Instruction Set (Revision 3.51) > + */ > > enum { > POOL32A = 0x00, > @@ -10268,9 +10278,10 @@ enum { > POOL16D = 0x13, > ORI32 = 0x14, > POOL32F = 0x15, > - POOL32S = 0x16, > - DADDIU32 = 0x17, > + POOL32S = 0x16, /* MIPS64 */ > + DADDIU32 = 0x17, /* MIPS64 */ > > + /* 0x1f is reserved */ > POOL32C = 0x18, > LWGP16 = 0x19, > LW16 = 0x1a, > @@ -10278,7 +10289,6 @@ enum { > XORI32 = 0x1c, > JALS32 = 0x1d, > ADDIUPC = 0x1e, > - POOL48A = 0x1f, > > /* 0x20 is reserved */ > RES_20 = 0x20, > @@ -10307,8 +10317,8 @@ enum { > B16 = 0x33, > ANDI32 = 0x34, > J32 = 0x35, > - SD32 = 0x36, > - LD32 = 0x37, > + SD32 = 0x36, /* MIPS64 */ > + LD32 = 0x37, /* MPIS64 */ > > /* 0x38 and 0x39 are reserved */ > RES_38 = 0x38, > -- > 1.7.3.4
diff --git a/target-mips/translate.c b/target-mips/translate.c index 01b48fa..1c0ff65 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, return n_bytes; } -/* microMIPS extension to MIPS32 */ +/* microMIPS extension to MIPS32/MIPS64 */ -/* microMIPS32 major opcodes */ +/* + * microMIPS32/microMIPS64 major opcodes + * + * 1. MIPS Architecture for Programmers Volume II-B: + * The microMIPS32 Instruction Set (Revision 3.05) + * + * Table 6.2 microMIPS32 Encoding of Major Opcode Field + * + * 2. MIPS Architecture For Programmers Volume II-A: + * The MIPS64 Instruction Set (Revision 3.51) + */ enum { POOL32A = 0x00, @@ -10268,9 +10278,10 @@ enum { POOL16D = 0x13, ORI32 = 0x14, POOL32F = 0x15, - POOL32S = 0x16, - DADDIU32 = 0x17, + POOL32S = 0x16, /* MIPS64 */ + DADDIU32 = 0x17, /* MIPS64 */ + /* 0x1f is reserved */ POOL32C = 0x18, LWGP16 = 0x19, LW16 = 0x1a, @@ -10278,7 +10289,6 @@ enum { XORI32 = 0x1c, JALS32 = 0x1d, ADDIUPC = 0x1e, - POOL48A = 0x1f, /* 0x20 is reserved */ RES_20 = 0x20, @@ -10307,8 +10317,8 @@ enum { B16 = 0x33, ANDI32 = 0x34, J32 = 0x35, - SD32 = 0x36, - LD32 = 0x37, + SD32 = 0x36, /* MIPS64 */ + LD32 = 0x37, /* MPIS64 */ /* 0x38 and 0x39 are reserved */ RES_38 = 0x38,
Hi all, I check MIPS microMIPS manual [1], and found the major opcode might be wrong. I add a comment to explicitly indicate what manual I am refering to, and according that manual I remove microMIPS32 major opcodes 0x1f. As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order MIPS ISA level or new revision of this microMIPS architecture. Quote from Johnson, they are belong MIPS64 [2]. Please review, thanks. [1] http://www.mips.com/products/architectures/micromips/#specifications MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set (Revision 3.05) MD00582-2B-microMIPS-AFP-03.05.pdf [2] http://www.mips.com/products/architectures/mips64/ MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set MD00087-2B-MIPS64BIS-AFP-03.51.pdf Signed-off-by: Chen Wei-Ren <chenwj@iis.sinica.edu.tw> --- target-mips/translate.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-)