@@ -83,6 +83,9 @@ m32c*-*-*)
cpu_type=m32c
tmake_file=t-fdpbit
;;
+aarch64*-*-*)
+ cpu_type=aarch64
+ ;;
alpha*-*-*)
cpu_type=alpha
;;
@@ -278,6 +281,16 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
esac
case ${host} in
+aarch64*-*-elf)
+ extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+ ;;
+aarch64*-*-linux*)
+ md_unwind_header=aarch64/linux-unwind.h
+ tmake_file="${tmake_file} ${cpu_type}/t-aarch64"
+ tmake_file="${tmake_file} ${cpu_type}/t-softfp t-softfp"
+ ;;
alpha*-*-linux*)
tmake_file="${tmake_file} alpha/t-alpha alpha/t-ieee t-crtfm alpha/t-linux"
extra_parts="$extra_parts crtfastmath.o"
@@ -0,0 +1,68 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+
+/* An executable stack is *not* required for these functions. */
+#if defined(__ELF__) && defined(__linux__)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
+# This file creates a stack frame for the contents of the .fini and
+# .init sections. Users may put any desired instructions in those
+# sections.
+
+#ifdef __ELF__
+#define TYPE(x) .type x,function
+#else
+#define TYPE(x)
+#endif
+
+ # Note - this macro is complemented by the FUNC_END macro
+ # in crtn.S. If you change this macro you must also change
+ # that macro match.
+.macro FUNC_START
+ # Create a stack frame and save any call-preserved registers
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+.endm
+
+ .section ".init"
+ .align 2
+ .global _init
+ TYPE(_init)
+_init:
+ FUNC_START
+
+
+ .section ".fini"
+ .align 2
+ .global _fini
+ TYPE(_fini)
+_fini:
+ FUNC_START
+
+# end of crti.S
@@ -0,0 +1,61 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 3, or (at your option) any
+# later version.
+#
+# This file is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# Under Section 7 of GPL version 3, you are granted additional
+# permissions described in the GCC Runtime Library Exception, version
+# 3.1, as published by the Free Software Foundation.
+#
+# You should have received a copy of the GNU General Public License and
+# a copy of the GCC Runtime Library Exception along with this program;
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+# <http://www.gnu.org/licenses/>.
+
+/* An executable stack is *not* required for these functions. */
+#if defined(__ELF__) && defined(__linux__)
+.section .note.GNU-stack,"",%progbits
+.previous
+#endif
+
+# This file just makes sure that the .fini and .init sections do in
+# fact return. Users may put any desired instructions in those sections.
+# This file is the last thing linked into any executable.
+
+ # Note - this macro is complemented by the FUNC_START macro
+ # in crti.S. If you change this macro you must also change
+ # that macro match.
+ #
+ # Note - we do not try any fancy optimizations of the return
+ # sequences here, it is just not worth it. Instead keep things
+ # simple. Restore all the save resgisters, including the link
+ # register and then perform the correct function return instruction.
+.macro FUNC_END
+ ldp x19, x20, [sp], #16
+ ldp x21, x22, [sp], #16
+ ldp x23, x24, [sp], #16
+ ldp x25, x26, [sp], #16
+ ldp x27, x28, [sp], #16
+ ldp x29, x30, [sp], #16
+ ret
+.endm
+
+
+ .section ".init"
+ ;;
+ FUNC_END
+
+ .section ".fini"
+ ;;
+ FUNC_END
+
+# end of crtn.S
@@ -0,0 +1,143 @@
+/* Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef inhibit_libc
+
+#include <signal.h>
+#include <sys/ucontext.h>
+
+#define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
+
+static _Unwind_Reason_Code
+aarch64_fallback_frame_state (struct _Unwind_Context *context,
+ _Unwind_FrameState * fs)
+{
+ /* The kernel creates an rt_sigframe on the stack immediately prior
+ to delivering a signal.
+
+ This structure must have the same shape as the linux kernel
+ equivalent. */
+ struct rt_sigframe
+ {
+ siginfo_t info;
+ struct ucontext uc;
+ };
+
+ struct rt_sigframe *rt_;
+ _Unwind_Ptr new_cfa;
+ unsigned *pc = context->ra;
+ struct sigcontext *sc;
+ struct _aarch64_ctx *extension_marker;
+ int i;
+
+ /* A signal frame will have a return address pointing to
+ __default_sa_restorer. This code is hardwired as:
+
+ 0xd2801168 movz x8, #0x8b
+ 0xd4000001 svc 0x0
+ */
+ if (pc[0] != 0xd2801168 || pc[1] != 0xd4000001)
+ {
+ return _URC_END_OF_STACK;
+ }
+
+ rt_ = context->cfa;
+ sc = &rt_->uc.uc_mcontext;
+
+/* This define duplicates the definition in aarch64.md */
+#define SP_REGNUM 31
+
+ new_cfa = (_Unwind_Ptr) sc;
+ fs->regs.cfa_how = CFA_REG_OFFSET;
+ fs->regs.cfa_reg = STACK_POINTER_REGNUM;
+ fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
+
+ for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
+ {
+ fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
+ fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
+ (_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
+ }
+
+ /* The core context may be extended with an arbitrary set of
+ additional contexts appended sequentially. Each additional
+ context contains a magic identifier and size in bytes. The size
+ field can be used to skip over unrecognized context extensions.
+ The end of the context sequence is marked by a context with magic
+ 0 or size 0. */
+ for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
+ extension_marker->magic;
+ extension_marker = (struct _aarch64_ctx *)
+ ((unsigned char *) extension_marker + extension_marker->size))
+ {
+ if (extension_marker->magic == FPSIMD_MAGIC)
+ {
+ struct fpsimd_context *ctx =
+ (struct fpsimd_context *) extension_marker;
+ int i;
+
+ for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
+ {
+ _Unwind_Sword offset;
+
+ fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
+
+ /* sigcontext contains 32 128bit registers for V0 to
+ V31. The kernel will have saved the contents of the
+ V registers. We want to unwind the callee save D
+ registers. Each D register comprises the least
+ significant half of the corresponding V register. We
+ need to offset into the saved V register dependent on
+ our endianness to find the saved D register. */
+
+ offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
+
+ /* The endianness adjustment code below expects that a
+ saved V register is 16 bytes. */
+ gcc_assert (sizeof (ctx->vregs[0]) == 16);
+#if defined (__AARCH64EB__)
+ offset = offset + 8;
+#endif
+ fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
+ }
+ }
+ else
+ {
+ /* There is context provided that we do not recognize! */
+ }
+ }
+
+ fs->regs.reg[31].how = REG_SAVED_OFFSET;
+ fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
+
+ fs->signal_frame = 1;
+
+ fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET;
+ fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset =
+ (_Unwind_Ptr) (sc->pc) - new_cfa;
+
+ fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
+
+ return _URC_NO_REASON;
+}
+
+#endif
@@ -0,0 +1,153 @@
+/* Machine description for AArch64 architecture.
+ Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#define _FP_W_TYPE_SIZE 64
+#define _FP_W_TYPE unsigned long
+#define _FP_WS_TYPE signed long
+#define _FP_I_TYPE int
+
+typedef int TItype __attribute__ ((mode (TI)));
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
+
+/* The type of the result of a floating point comparison. This must
+ match __libgcc_cmp_return__ in GCC for the target. */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_Q(R,X,Y) \
+ _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
+#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
+#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
+#define _FP_NANSIGN_S 0
+#define _FP_NANSIGN_D 0
+#define _FP_NANSIGN_Q 0
+
+#define _FP_KEEPNANFRACP 1
+
+/* This appears to be in line with the VFP conventions in the v7-a
+ ARM-ARM. Need to check with the v8 version. */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
+ do { \
+ if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
+ && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
+ { \
+ R##_s = Y##_s; \
+ _FP_FRAC_COPY_##wc(R,Y); \
+ } \
+ else \
+ { \
+ R##_s = X##_s; \
+ _FP_FRAC_COPY_##wc(R,X); \
+ } \
+ R##_c = FP_CLS_NAN; \
+ } while (0)
+
+#define FP_EX_INVALID 0x01
+#define FP_EX_DIVZERO 0x02
+#define FP_EX_OVERFLOW 0x04
+#define FP_EX_UNDERFLOW 0x08
+#define FP_EX_INEXACT 0x10
+
+#define FP_HANDLE_EXCEPTIONS \
+ do { \
+ const float fp_max = __FLT_MAX__; \
+ const float fp_min = __FLT_MIN__; \
+ const float fp_1e32 = 1.0e32f; \
+ const float fp_zero = 0.0; \
+ const float fp_one = 1.0; \
+ unsigned fpsr; \
+ if (_fex & FP_EX_INVALID) \
+ { \
+ __asm__ __volatile__ ("fdiv\ts0, %s0, %s0" \
+ : \
+ : "w" (fp_zero) \
+ : "s0"); \
+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \
+ } \
+ if (_fex & FP_EX_DIVZERO) \
+ { \
+ __asm__ __volatile__ ("fdiv\ts0, %s0, %s1" \
+ : \
+ : "w" (fp_one), "w" (fp_zero) \
+ : "s0"); \
+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \
+ } \
+ if (_fex & FP_EX_OVERFLOW) \
+ { \
+ __asm__ __volatile__ ("fadd\ts0, %s0, %s1" \
+ : \
+ : "w" (fp_max), "w" (fp_1e32) \
+ : "s0"); \
+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \
+ } \
+ if (_fex & FP_EX_UNDERFLOW) \
+ { \
+ __asm__ __volatile__ ("fmul\ts0, %s0, %s0" \
+ : \
+ : "w" (fp_min) \
+ : "s0"); \
+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \
+ } \
+ if (_fex & FP_EX_INEXACT) \
+ { \
+ __asm__ __volatile__ ("fsub\ts0, %s0, %s1" \
+ : \
+ : "w" (fp_max), "w" (fp_one) \
+ : "s0"); \
+ __asm__ __volatile__ ("mrs\t%0, fpsr" : "=r" (fpsr)); \
+ } \
+ } while (0)
+
+
+#define FP_RND_NEAREST 0
+#define FP_RND_ZERO 0xc00000
+#define FP_RND_PINF 0x400000
+#define FP_RND_MINF 0x800000
+
+#define _FP_DECL_EX \
+ unsigned long int _fpcr __attribute__ ((unused)) = FP_RND_NEAREST
+
+#define FP_INIT_ROUNDMODE \
+ do { \
+ __asm__ __volatile__ ("mrs %0, fpcr" \
+ : "=r" (_fpcr)); \
+ } while (0)
+
+#define FP_ROUNDMODE (_fpcr & 0xc00000)
+
+#define __LITTLE_ENDIAN 1234
+#define __BIG_ENDIAN 4321
+
+#if defined __AARCH64EB__
+# define __BYTE_ORDER __BIG_ENDIAN
+#else
+# define __BYTE_ORDER __LITTLE_ENDIAN
+#endif
+
+
+/* Define ALIASNAME as a strong alias for NAME. */
+# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+# define _strong_alias(name, aliasname) \
+ extern __typeof (name) aliasname __attribute__ ((alias (#name)));
@@ -0,0 +1,57 @@
+/* Machine description for AArch64 architecture.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+void
+__aarch64_sync_cache_range (const void *base, const void *end)
+{
+ unsigned icache_lsize;
+ unsigned dcache_lsize;
+ static unsigned int cache_info = 0;
+ const char *address;
+
+ if (! cache_info)
+ /* CTR_EL0 [3:0] contains log2 of icache line size in words.
+ CTR_EL0 [19:16] contains log2 of dcache line size in words. */
+ asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
+
+ icache_lsize = 4 << (cache_info & 0xF);
+ dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
+
+ /* Loop over the address range, clearing one cache line at once.
+ Data cache must be flushed to unification first to make sure the
+ instruction cache fetches the updated data. 'end' is exclusive,
+ as per the GNU definition of __clear_cache. */
+
+ for (address = base; address < (const char *) end; address += dcache_lsize)
+ asm volatile ("dc\tcvau, %0"
+ :
+ : "r" (address)
+ : "memory");
+
+ asm volatile ("dsb\tish" : : : "memory");
+
+ for (address = base; address < (const char *) end; address += icache_lsize)
+ asm volatile ("ic\tivau, %0"
+ :
+ : "r" (address)
+ : "memory");
+
+ asm volatile ("dsb\tish; isb" : : : "memory");
+}
@@ -0,0 +1,21 @@
+# Machine description for AArch64 architecture.
+# Copyright (C) 2012 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+LIB2ADD += $(srcdir)/config/aarch64/sync-cache.c
@@ -0,0 +1,7 @@
+softfp_float_modes := tf
+softfp_int_modes := si di ti
+softfp_extensions := sftf dftf
+softfp_truncations := tfsf tfdf
+softfp_exclude_libgcc2 := n
+
+TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes
This patch provides the AArch64 libgcc port, it contains both the required configury adjustment to config.host and the new files introduced by the AArch64 port. Proposed ChangeLog: * config.host (aarch64*-*-elf, aarch64*-*-linux*): New. * config/aarch64/crti.S: New file. * config/aarch64/crtn.S: New file. * config/aarch64/linux-unwind.h: New file. * config/aarch64/sfp-machine.h: New file. * config/aarch64/sync-cache.c: New file. * config/aarch64/t-aarch64: New file. * config/aarch64/t-softfp: New file.