diff mbox

[Precise,SRU] drm/i915: Remove too early plane enable on pre-PCH hardware

Message ID 507D7E3A.1030502@canonical.com
State New
Headers show

Commit Message

Chris J Arges Oct. 16, 2012, 3:33 p.m. UTC 
SRU Justification:

Impact:
Users with an Intel GMA X3000 graphics card experience display
corruption when using Precise. This occurs when there is a resolution
change.

Fix:
Commit c7bd4c25650704d4d065eb4ce2a122d2a80ce804 fixes this issue, and is
currently in Quantal. Cherry-picking this patch causes the display to
work properly even after extensive resolution changes.

Testcase:
Change resolution repeatedly using xrandr on a computer with the Intel
GMA X3000 graphics card. Check for display corruption.

BugLink: http://bugs.launchpad.net/bugs/949130

Comments

Seth Forshee Oct. 16, 2012, 4:16 p.m. UTC | #1
Colin Ian King Oct. 16, 2012, 4:23 p.m. UTC | #2 
On 16/10/12 16:33, Chris J Arges wrote:
> SRU Justification:
>
> Impact:
> Users with an Intel GMA X3000 graphics card experience display
> corruption when using Precise. This occurs when there is a resolution
> change.
>
> Fix:
> Commit c7bd4c25650704d4d065eb4ce2a122d2a80ce804 fixes this issue, and is
> currently in Quantal. Cherry-picking this patch causes the display to
> work properly even after extensive resolution changes.
>
> Testcase:
> Change resolution repeatedly using xrandr on a computer with the Intel
> GMA X3000 graphics card. Check for display corruption.
>
> BugLink: http://bugs.launchpad.net/bugs/949130
>
>
>
Acked-by: Colin Ian King <colin.king@canonical.com>
Tim Gardner Oct. 16, 2012, 5:31 p.m. UTC | #3 
This is not a clean cherry-pick on master-next. Please have another look.
diff mbox

Patch

From e0ee9beceb24baaadb2675d0bb172afc07cbb073 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed, 10 Oct 2012 12:25:45 -0500
Subject: [PATCH] drm/i915: Remove too early plane enable on pre-PCH hardware

Enabling the plane before we have assigned valid address means that it
will access random PTE (often with conflicting memory types) and cause
GPU lockups. However, enabling the plane too early appears to workaround
a number of bugs in our modesetting code.

Cc: Franz Melchior <melchior.franz@gmail.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=39947
References: https://bugs.freedesktop.org/show_bug.cgi?id=41091
References: https://bugs.freedesktop.org/show_bug.cgi?id=49041
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

(cherry-picked from c7bd4c25650704d4d065eb4ce2a122d2a80ce804)

BugLink: http://bugs.launchpad.net/bugs/949130

Signed-off-by: Chris J Arges <chris.j.arges@canonical.com>
---
 drivers/gpu/drm/i915/intel_display.c |    1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a1e9eb9..6374be5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5192,7 +5192,6 @@  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));
-	intel_enable_plane(dev_priv, plane, pipe);
 
 	ret = intel_pipe_set_base(crtc, x, y, old_fb);
 
-- 
1.7.9.5