@@ -37,7 +37,7 @@
#define CONFIG_SYS_COREBOOT
#undef CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
-
+#define CONFIG_NO_RESET_CODE
/*-----------------------------------------------------------------------
* Watchdog Configuration
@@ -45,6 +45,10 @@
#undef CONFIG_WATCHDOG
#undef CONFIG_HW_WATCHDOG
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
+
/*-----------------------------------------------------------------------
* Real Time Clock Configuration
*/
Coreboot boards have an LPC TPM connected, so enable this. We also need to skip the reset code. Signed-off-by: Simon Glass <sjg@chromium.org> --- include/configs/coreboot.h | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)