| Message ID | 1349117653-19380-1-git-send-email-aurelien@aurel32.net |
|---|---|
| State | New |
| Headers | show |
On Mon, Oct 1, 2012 at 10:54 PM, Aurelien Jarno <aurelien@aurel32.net> wrote: > Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift > are optimized in tcg/tcg-op.h there is no need to do it in > target-xtensa/translate.c. > > Cc: Max Filippov <jcmvbkbc@gmail.com> > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> > --- > target-xtensa/translate.c | 22 ++-------------------- > 1 file changed, 2 insertions(+), 20 deletions(-) > > v1 -> v2: also remove the test on shiftimm to select either a shift or > a move. Acked-by: Max Filippov <jcmvbkbc@gmail.com>
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index b9acd70..82e8ccc 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1829,26 +1829,8 @@ static void disas_xtensa_insn(DisasContext *dc) int maskimm = (1 << (OP2 + 1)) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); - - if (shiftimm) { - tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); - } else { - tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); - } - - switch (maskimm) { - case 0xff: - tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp); - break; - - case 0xffff: - tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp); - break; - - default: - tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); - break; - } + tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); + tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); tcg_temp_free(tmp); } break;
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift are optimized in tcg/tcg-op.h there is no need to do it in target-xtensa/translate.c. Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target-xtensa/translate.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) v1 -> v2: also remove the test on shiftimm to select either a shift or a move.